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platform: Update Nuclei ux600 platform support
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Changes are made to support our FPGA evaluation board,
it has DDR memory(0xA0000000-0xB0000000).

* Adapt the config.mk to match FPGA evaluation board DDR memory address
* Since the RISC-V CPU core frequency of FPGA might change, so we use the
  fixed TIMER frequency to measure the real CPU core frequency.
* And the UART baudrate has to set to 57600bps for Nuclei FPGA evaluation
  board when CPU core frequency is about 8MHz, otherwise the UART input
  will not work correctly.

Signed-off-by: Huaqi Fang <578567190@qq.com>
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fanghuaqi committed Jun 12, 2020
1 parent 32f87e5 commit 4378320
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Showing 2 changed files with 79 additions and 9 deletions.
8 changes: 4 additions & 4 deletions platform/nuclei/ux600/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -19,12 +19,12 @@ platform-runcmd = xl_spike \
$(build_dir)/platform/nuclei/ux600/firmware/fw_payload.elf

# Blobs to build
FW_TEXT_START=0x80000000
FW_TEXT_START=0xA0000000
FW_DYNAMIC=y
FW_JUMP=y

FW_JUMP_ADDR=0x80200000
FW_JUMP_FDT_ADDR=0x88000000
FW_JUMP_ADDR=0xA0200000
FW_JUMP_FDT_ADDR=0xA8000000
FW_PAYLOAD=y
FW_PAYLOAD_OFFSET=0x200000
FW_PAYLOAD_FDT_ADDR=0x88000000
FW_PAYLOAD_FDT_ADDR=0xA8000000
80 changes: 75 additions & 5 deletions platform/nuclei/ux600/platform.c
Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,12 @@
/* clang-format off */

#define UX600_HART_COUNT 1

#define UX600_SYS_CLK 1000000000
#define UX600_TIMER_FREQ 32768

/* Nuclei timer base address */
#define UX600_NUCLEI_TIMER_ADDR 0x2000000
#define UX600_NUCLEI_TIMER_MSFTRST_OFS 0xFF0
#define UX600_NUCLEI_TIMER_MSFTRST_KEY 0x80000A5F
/* The clint compatiable timer offset is 0x1000 against nuclei timer */
#define UX600_CLINT_TIMER_ADDR (UX600_NUCLEI_TIMER_ADDR + 0x1000)

Expand All @@ -39,9 +40,20 @@
#define UX600_UART1_ADDR 0x10023000

#define UX600_DEBUG_UART UX600_UART0_ADDR
#define UX600_UART_BAUDRATE 115200

#ifndef UX600_UART_BAUDRATE
#define UX600_UART_BAUDRATE 57600
#endif

#define UX600_GPIO_ADDR 0x10012000
#define UX600_GPIO_IOF_EN_OFS 0x38
#define UX600_GPIO_IOF_SEL_OFS 0x3C
#define UX600_GPIO_IOF_UART0_MASK 0x00030000

#define UX600_TIMER_VALUE() readl((void *)UX600_NUCLEI_TIMER_ADDR)

/* clang-format on */
static u32 ux600_clk_freq = 8000000;

static struct plic_data plic = {
.addr = UX600_PLIC_ADDR,
Expand All @@ -54,6 +66,60 @@ static struct clint_data clint = {
.hart_count = UX600_HART_COUNT,
.has_64bit_mmio = TRUE,
};
static u32 measure_cpu_freq(u32 n)
{
u32 start_mtime, delta_mtime;
u32 mtime_freq = UX600_TIMER_FREQ;
u32 tmp = (u32)UX600_TIMER_VALUE();
u32 start_mcycle, delta_mcycle, freq;

/* Don't start measuring until we see an mtime tick */
do {
start_mtime = (u32)UX600_TIMER_VALUE();
} while (start_mtime == tmp);

start_mcycle = csr_read(mcycle);

do {
delta_mtime = (u32)UX600_TIMER_VALUE() - start_mtime;
} while (delta_mtime < n);

delta_mcycle = csr_read(mcycle) - start_mcycle;

freq = (delta_mcycle / delta_mtime) * mtime_freq
+ ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;

return freq;
}

static u32 ux600_get_clk_freq(void)
{
u32 cpu_freq;

/* warm up */
measure_cpu_freq(1);
/* measure for real */
cpu_freq = measure_cpu_freq(100);

return cpu_freq;
}

static int ux600_early_init(bool cold_boot)
{
u32 regval;

/* Measure CPU Frequency using Timer */
ux600_clk_freq = ux600_get_clk_freq();

/* Init GPIO UART pinmux */
regval = readl((void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_SEL_OFS)) &
~UX600_GPIO_IOF_UART0_MASK;
writel(regval, (void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_SEL_OFS));
regval = readl((void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_EN_OFS)) |
UX600_GPIO_IOF_UART0_MASK;
writel(regval, (void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_EN_OFS));
return 0;
}

static void ux600_modify_dt(void *fdt)
{
Expand All @@ -75,7 +141,7 @@ static int ux600_final_init(bool cold_boot)

static int ux600_console_init(void)
{
return sifive_uart_init(UX600_DEBUG_UART, UX600_SYS_CLK,
return sifive_uart_init(UX600_DEBUG_UART, ux600_clk_freq,
UX600_UART_BAUDRATE);
}

Expand Down Expand Up @@ -122,11 +188,15 @@ static int ux600_timer_init(bool cold_boot)

static int ux600_system_reset(u32 type)
{
/* For now nothing to do. */
/* Reset system using MSFTRST register in Nuclei Timer. */
writel(UX600_NUCLEI_TIMER_MSFTRST_KEY, (void *)(UX600_NUCLEI_TIMER_ADDR
+ UX600_NUCLEI_TIMER_MSFTRST_OFS));
while(1);
return 0;
}

const struct sbi_platform_operations platform_ops = {
.early_init = ux600_early_init,
.final_init = ux600_final_init,
.console_putc = sifive_uart_putc,
.console_getc = sifive_uart_getc,
Expand Down

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