core: interrupts: add gic_spi_release_to_ns API to reset the properties

of an interrupt

This patch introduces gic_spi_release_to_ns API to release an interrupt
to Non secure settings. This functionality is essential for scenarios
where a specific interrupt needs to be dynamically set to either Group
1 Secure (G1S) or Group 1 Non-Secure (G1NS) at different times.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>

core/drivers/gic.c

@@ -858,6 +858,30 @@ void gic_dump_state(void)
 	}
 }
 
+void gic_spi_release_to_ns(size_t it)
+{
+	struct gic_data *gd = &gic_data;
+	size_t idx = it / NUM_INTS_PER_REG;
+	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
+
+	assert(it < gd->max_it && it >= GIC_SPI_BASE);
+	/* Assert it's already disabled */
+	assert(!gic_it_is_enabled(gd, it));
+	/* Assert it's secure to start with */
+	assert(!gic_it_get_group(gd, it));
+
+	gic_it_set_cpu_mask(gd, it, 0);
+	gic_it_set_prio(gd, it, GIC_SPI_PRI_NS_EL1);
+
+	/* Clear pending status */
+	io_write32(gd->gicd_base + GICD_ICPENDR(idx), mask);
+	/* Assign it to NS Group1 */
+	io_setbits32(gd->gicd_base + GICD_IGROUPR(idx), mask);
+#if defined(CFG_ARM_GICV3)
+	io_clrbits32(gd->gicd_base + GICD_IGROUPMODR(idx), mask);
+#endif
+}
+
 static void __maybe_unused gic_native_itr_handler(void)
 {
 	struct gic_data *gd = &gic_data;

core/include/drivers/:q

@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2016, Linaro Limited
+ * Copyright (c) 2014, STMicroelectronics International N.V.
+ */
+
+#ifndef __DRIVERS_GIC_H
+#define __DRIVERS_GIC_H
+#include <types_ext.h>
+#include <kernel/interrupt.h>
+
+#if defined(CFG_ARM_GICV3)
+#define GIC_DIST_REG_SIZE	0x10000
+#define GIC_CPU_REG_SIZE	0x10000
+#else
+#define GIC_DIST_REG_SIZE	0x1000
+#define GIC_CPU_REG_SIZE	0x1000
+#endif
+
+#define GIC_PPI_BASE		U(16)
+#define GIC_SPI_BASE		U(32)
+
+#define GIC_SGI_TO_ITNUM(x)	(x)
+#define GIC_PPI_TO_ITNUM(x)	((x) + GIC_PPI_BASE)
+#define GIC_SPI_TO_ITNUM(x)	((x) + GIC_SPI_BASE)
+
+/*
+ * Default lowest ID for secure SGIs, note that this does not account for
+ * interrupts donated to non-secure world with gic_init_donate_sgi_to_ns().
+ */
+#define GIC_SGI_SEC_BASE	8
+/* Max ID for secure SGIs */
+#define GIC_SGI_SEC_MAX		15
+/* Default IRQ priority for SPIs in Non-Sec EL1 */
+#define GIC_SPI_PRI_NS_EL1	0xa0
+
+/*
+ * The two gic_init() and gic_init_v3() functions initializes the struct
+ * gic_data which is then used by the other functions. These two functions
+ * also initializes the GIC and are only supposed to be called from the
+ * primary boot CPU.
+ */
+void gic_init_v3(paddr_t gicc_base_pa, paddr_t gicd_base_pa,
+		 paddr_t gicr_base_pa);
+static inline void gic_init(paddr_t gicc_base_pa, paddr_t gicd_base_pa)
+{
+	gic_init_v3(gicc_base_pa, gicd_base_pa, 0);
+}
+
+/* Donates one of the secure SGIs to normal world */
+void gic_init_donate_sgi_to_ns(size_t it);
+
+/*
+ * Does per-CPU specific GIC initialization, should be called by all
+ * secondary CPUs when booting.
+ */
+void gic_init_per_cpu(void);
+
+/* Print GIC state to console */
+void gic_dump_state(void);
+
+/* Release the property for a shared peripheral interrupt */
+void gic_spi_release_to_ns(size_t it);
+#endif /*__DRIVERS_GIC_H*/

core/include/drivers/gic.h

@@ -31,6 +31,8 @@
 #define GIC_SGI_SEC_BASE	8
 /* Max ID for secure SGIs */
 #define GIC_SGI_SEC_MAX		15
+/* Default IRQ priority for SPIs in Non-Sec EL1 */
+#define GIC_SPI_PRI_NS_EL1	0xa0
 
 /*
  * The two gic_init() and gic_init_v3() functions initializes the struct
@@ -56,4 +58,7 @@ void gic_init_per_cpu(void);
 
 /* Print GIC state to console */
 void gic_dump_state(void);
+
+/* Release the property for a shared peripheral interrupt */
+void gic_spi_release_to_ns(size_t it);
 #endif /*__DRIVERS_GIC_H*/