core: clarify comment on some memory identification magics

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
OP-TEE · Sep 20, 2017 · ed51c4a · ed51c4a
1 parent a3ada52
commit ed51c4a
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/core/arch/arm/include/mm/core_mmu.h b/core/arch/arm/include/mm/core_mmu.h
@@ -101,10 +101,10 @@
  * MEM_AREA_COHERENT_FLAT: flat mapped uncached RAM (secure, read/write)
  * MEM_AREA_TA_RAM:   Secure RAM where teecore loads/exec TA instances.
  * MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE.
- * MEM_AREA_RAM_NSEC: NonSecure RAM storing data
- * MEM_AREA_RAM_SEC:  Secure RAM storing some secrets
- * MEM_AREA_IO_NSEC:  NonSecure HW mapped registers
- * MEM_AREA_IO_SEC:   Secure HW mapped registers
+ * MEM_AREA_RAM_NSEC: NonSecure RAM storing data, cached, read/write.
+ * MEM_AREA_RAM_SEC:  Secure RAM storing some secrets, cached, read/write.
+ * MEM_AREA_IO_NSEC:  NonSecure noncached read/write (i.e HW mapped registers)
+ * MEM_AREA_IO_SEC:   Secure noncached read/write (i.e HW mapped registers)
  * MEM_AREA_RES_VASPACE: Reserved virtual memory space
  * MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers
  * MEM_AREA_TA_VASPACE: TA va space, only used with phys_to_virt()