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Support for *flat mapped* coherent secure RAM #1533

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Support for *flat mapped* coherent secure RAM #1533

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87d70c3
core: review static mapping layout sequence
etienne-lms Nov 13, 2017
15490e9
core: map registered flat mapped coherent memory
etienne-lms Nov 15, 2017
9eb4643
core: linkable flat mapped coherent memory section
etienne-lms Nov 13, 2017
5a75fc8
core: clean log in memory layout dumps
etienne-lms Sep 19, 2017
9051256
core: clarify comment on some memory identification magics
etienne-lms Sep 19, 2017
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11 changes: 7 additions & 4 deletions core/arch/arm/include/mm/core_mmu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -114,13 +114,14 @@
* MEM_AREA_TEE_RAM_RO: core private read-only/non-executable memory (secure)
* MEM_AREA_TEE_RAM_RW: core private read/write/non-executable memory (secure)
* MEM_AREA_TEE_COHERENT: teecore coherent RAM (secure, reserved to TEE)
* MEM_AREA_COHERENT_FLAT: flat mapped uncached RAM (secure, reserved to TEE)
* MEM_AREA_TEE_ASAN: core address sanitizer RAM (secure, reserved to TEE)
* MEM_AREA_TA_RAM: Secure RAM where teecore loads/exec TA instances.
* MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE.
* MEM_AREA_RAM_NSEC: NonSecure RAM storing data
* MEM_AREA_RAM_SEC: Secure RAM storing some secrets
* MEM_AREA_IO_NSEC: NonSecure HW mapped registers
* MEM_AREA_IO_SEC: Secure HW mapped registers
* MEM_AREA_RAM_NSEC: NonSecure RAM storing data, cached, read/write.
* MEM_AREA_RAM_SEC: Secure RAM storing some secrets, cached, read/write.
* MEM_AREA_IO_NSEC: NonSecure noncached read/write (i.e HW mapped registers)
* MEM_AREA_IO_SEC: Secure noncached read/write (i.e HW mapped registers)
* MEM_AREA_RES_VASPACE: Reserved virtual memory space
* MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers
* MEM_AREA_TA_VASPACE: TA va space, only used with phys_to_virt()
Expand All @@ -133,6 +134,7 @@ enum teecore_memtypes {
MEM_AREA_TEE_RAM_RO,
MEM_AREA_TEE_RAM_RW,
MEM_AREA_TEE_COHERENT,
MEM_AREA_COHERENT_FLAT,
MEM_AREA_TEE_ASAN,
MEM_AREA_TA_RAM,
MEM_AREA_NSEC_SHM,
Expand All @@ -158,6 +160,7 @@ static inline const char *teecore_memtype_name(enum teecore_memtypes type)
[MEM_AREA_TEE_RAM_RW] = "TEE_RAM_RW",
[MEM_AREA_TEE_ASAN] = "TEE_ASAN",
[MEM_AREA_TEE_COHERENT] = "TEE_COHERENT",
[MEM_AREA_COHERENT_FLAT] = "COHERENT_FLAT",
[MEM_AREA_TA_RAM] = "TA_RAM",
[MEM_AREA_NSEC_SHM] = "NSEC_SHM",
[MEM_AREA_RAM_NSEC] = "RAM_NSEC",
Expand Down
24 changes: 24 additions & 0 deletions core/arch/arm/kernel/kern.ld.S
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Original file line number Diff line number Diff line change
Expand Up @@ -70,9 +70,28 @@
OUTPUT_FORMAT(CFG_KERN_LINKER_FORMAT)
OUTPUT_ARCH(CFG_KERN_LINKER_ARCH)

#define LINK_COHERENT_FLATMAP_RAM \
. = COHERENT_FLATMAP_BASE; \
.coherent (NOLOAD) : { \
ASSERT(!(. & (SMALL_PAGE_SIZE - 1)), \
"Coherent memory start is not aligned"); \
__coherent_start = .; \
KEEP(*(.coherent_ram)); \
. = ALIGN(SMALL_PAGE_SIZE); \
__coherent_end = .; \
ASSERT(COHERENT_FLATMAP_SIZE >= \
(. - __coherent_start), \
"Coherent memory is undersized"); \
}

ENTRY(_start)
SECTIONS
{
#if defined(COHERENT_FLATMAP_BASE) && COHERENT_FLATMAP_BASE < TEE_TEXT_VA_START
LINK_COHERENT_FLATMAP_RAM
ASSERT(. <= TEE_TEXT_VA_START, "Coherent memory is oversized")
#endif

. = TEE_TEXT_VA_START;
#ifdef ARM32
ASSERT(!(TEE_TEXT_VA_START & 31), "text start should align to 32bytes")
Expand Down Expand Up @@ -440,6 +459,11 @@ SECTIONS
__flatmap_unpg_rw_size = _end_of_ram - __flatmap_unpg_rw_start;
#endif

#if defined(COHERENT_FLATMAP_BASE) && COHERENT_FLATMAP_BASE > CFG_TEE_RAM_START
ASSERT(. <= COHERENT_FLATMAP_BASE, "Coherent memory does not fit")
LINK_COHERENT_FLATMAP_RAM
#endif

/DISCARD/ : {
/* Strip unnecessary stuff */
*(.comment .note .eh_frame)
Expand Down
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