Add i.MX PSCI CPU off and update i.MX6UL #1577

MrVan · 2017-06-02T08:27:06Z

This patch reset contains the two patches in #1570 which has not been merged. So post all the patches together to avoid function break and requesting comments. After comments addressed and #1570 merged, I'll drop the two patches and resend the pull request.

In this patchset, imx6ul-regs.h imx6-regs.h are replaced by one imx-regs.h. The 6UL TEE mapping is refined to 0x9E000000 and 32M used. The original code use 0x9C000000, and 48M used. Add psci helper function used for psci cpu off and add the support for i.MX6Q-SDB. Testing results shows works well with Linux in non-secure world.

MrVan · 2017-06-02T12:05:23Z

Updated with dropping the two patches merged by #1570

etienne-lms

Very nice change.
Looking a atf psci library integration in optee, i faced the same required sequence: here (edited: in my case,
cache is already off when entering arch_cpu_power_down).

etienne-lms · 2017-06-02T10:38:48Z

core/arch/arm/plat-imx/imx-regs.h

+#define IOMUXC_GPR10_OFFSET		0x28
+
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET	5
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK		(0x3f << 5)


style: prefer GENMASK_32(10, 5)

and same below, prefer use of BIT() and GENMASK_32().

etienne-lms · 2017-06-02T10:44:30Z

core/arch/arm/sm/psci-helper.S

+FUNC psci_enable_smp, :
+UNWIND(	.fnstart)
+	read_actlr r0
+	orr	r0, r0, #(1 << 6)


style: can use ACTLR_SMP from arm32.h

etienne-lms · 2017-06-02T13:06:58Z

core/arch/arm/sm/psci-helper.S

+
+	bl	psci_disable_smp
+
+	pop	{lr}


minor; suggest pop {pc}

No. I use pop {lr}; bx {lr} to switch between ARM/THUMB. pop {pc} may cause issue if now is in ARM mode.

Perhaps it can cause an issue on pre-ARMv7 architectures, but in ARMv7 I haven't seen an issue related to this.

ok. I'll give a test on this. If ok, I'll switch to use pop {pc}

etienne-lms · 2017-06-02T13:08:12Z

core/arch/arm/sm/psci-helper.S

+
+	/* Disable Cache */
+	read_sctlr r0
+	bic	r0, r0, #(1 << 2)


suggest SCTLR_C from arm32.h

etienne-lms · 2017-06-02T13:08:42Z

core/arch/arm/sm/psci-helper.S

+ *
+ * flush dcache all to PoC
+ */
+FUNC psci_armv7_flush_dcache_all , :


may i claim a 2nd look at this?
against core native cache support.

This needs to flush the inner cache only. It so could be renamed cpu_armv7_flush_inner_dcache_all() ?

this is ok for me. I would use psci_armv7_flush_inner_dcache_all.

Doesn't this function rather belong in core/arch/arm/kernel/ssvce_a32.S?

agree. I just checked core/arch/arm/kernel/ssvce_a32.S, seems arm_cl1_d_cleanbysetway is also for this, but arm_cl1_d_cleanbysetway is a simplied version. I may need to update ssvce_a32.S.

etienne-lms · 2017-06-02T13:17:15Z

core/arch/arm/sm/psci-helper.S

+
+	bl	psci_armv7_flush_dcache_all
+
+	clrex


clrex really needed ? ___ edited, actually, this was a question :(

Actually I have no good idea on this. From my experience of PSCI U-Boot interface, I think this is needed. I am not sure this is correct or not: This core may execute LDREX/STREX before, so when offline, need to execute CLREX to clear-exclusive.

jenswi-linaro · 2017-06-02T14:06:55Z

core/arch/arm/plat-imx/psci.c

+
+	imx_set_src_gpr(core_id, ~0);
+
+	asm volatile (


Provided that we had a wfi() function (not that hard to add) this could could be written as:

thread_mask_exceptions(THREAD_EXCP_ALL); while (true) wfi();

Thanks. Fix in next version.

jenswi-linaro · 2017-06-02T14:07:35Z

core/arch/arm/plat-imx/psci.c

+	vaddr_t gpr5 = core_mmu_get_va(IOMUXC_BASE, MEM_AREA_IO_SEC) +
+		IOMUXC_GPR5_OFFSET;
+	uint32_t cpu, val;
+	uint32_t wfi;


Type should be bool

jenswi-linaro · 2017-06-02T14:08:07Z

core/arch/arm/plat-imx/psci.c

+
+	cpu = affinity;
+
+	wfi = !!(read32(gpr5) & ARM_WFI_STAT_MASK(cpu));


No need to normalize a bool as that's done by the compiler as required by the standard.

Fix in next version

jenswi-linaro · 2017-06-02T14:09:53Z

core/arch/arm/plat-imx/psci.c

+
+	wfi = !!(read32(gpr5) & ARM_WFI_STAT_MASK(cpu));
+
+	if ((imx_get_src_gpr(cpu) == 0) || !wfi)


!imx_get_src_gpr(cpu) is the preferred style.

This is not to check false or true, I just check whether its value is 0 or non-zero, I prefer use == here.

jenswi-linaro · 2017-06-05T08:40:19Z

core/arch/arm/sm/psci-helper.S

+
+	bl	psci_disable_smp
+
+	pop	{lr}


Perhaps it can cause an issue on pre-ARMv7 architectures, but in ARMv7 I haven't seen an issue related to this.

jenswi-linaro · 2017-06-07T10:26:55Z

For information, I've started to (re-)import the cache maintenance routines from ARM-TF (lib/aarch32/cache_helpers.S and lib/aarch64/cache_helpers.S). I'll create a pull request in due time.

MrVan · 2017-06-07T14:01:40Z

@jenswi-linaro that's great. Then I'll directly use your new code in my psci code.

MrVan · 2017-06-08T01:13:20Z

@jenswi-linaro one more question, about the code importing from ARM-TF, will code be merged before 2.5.0? I would like to upstream more i.mx psci code before 2.5.0. If you do not plan to merge you patch before 2.5.0, I may still need to update ssvce_a32.S.

jenswi-linaro · 2017-06-08T07:18:08Z

Please go ahead with this PR, waiting for my updates will only delay this.

MrVan · 2017-06-10T08:51:48Z

@etienne-lms @jenswi-linaro Updated. Use cpu_armv7_flush_inner_dcache_all and move to ssvce_a32.S. use macros but not number bit shift. wfi function is not added, still use asm code to do dead loop wfi. I added a new more patches in this patchset, switch to use REE time for 6UL, add platform early init code for A7 core, add 6ULL EVK.

During my test, I met failure: optee_test/host/xtest/regression_4000.c:2380: Expression "out_size == ciph_cases[n].in_incr" (0 == 13) is false regression_4003_NO_XTS.5 FAILED, using latest client/os/test.

jforissier · 2017-06-12T06:54:53Z

During my test, I met failure: optee_test/host/xtest/regression_4000.c:2380: Expression "out_size == ciph_cases[n].in_incr" (0 == 13) is false regression_4003_NO_XTS.5 FAILED, using latest client/os/test.

This is likely a problem with the build, something not cleaned properly. Please make sure there is no libutee.a left from a previous build, and also make sure the crypt TA is properly rebuilt (re-linked against the new libutee.a). I sometimes do rm -rf optee_os/out optee_test/out when in doubt...

etienne-lms

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

commit1 core: arm: mx6ulevk: refine the tee address map:
commit3 arm: ssvce_a32: introduce cpu_armv7_flush_inner_dcache_all
commit5 (minor comments) core: arm: imx: use one imx-regs.h file
commit7 core: imx6ul: switch to use CFG_SECURE_TIME_SOURCE_REE
commit8 (minor comments) core: arm: imx6ul: add platform early init code
commit9 core: arm: imx: add 6ULL EVK support

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

commit2: core: arm32_macros: add macros

Still open (to me)

commit4 core: arm: psci: add helper functions
some comments. I am checking some dmb/isb. But looks ok.
commit6 core: arm: imx support psci off and affinity
Some comments + minor comment on commit comment: s/Introuduce/Introduce/, s/is use/is used/

etienne-lms · 2017-06-12T07:54:42Z

core/arch/arm/plat-imx/imx.h

+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+


#ifndef PLAT_IMX_IMX_H #define PLAT_IMX_IMX_H ... #endif

Fix in next version

etienne-lms · 2017-06-12T07:59:09Z

core/arch/arm/plat-imx/a7_plat_init.S

-#define DRAM0_BASE			0x80000000
-#define DRAM0_SIZE			0x20000000
+	movw r0, #0x0040
+	movt r0, #0x0000


minor: suggested mov_imm r0, 0x00000040
and below mov_imm r0, 0x00040C00
Macros for these magics would be welcome.

yeah. Thanks.

etienne-lms · 2017-06-12T08:14:18Z

core/arch/arm/include/sm/psci.h

@@ -58,3 +58,5 @@ int psci_node_hw_state(uint32_t cpu_id, uint32_t power_level);
 int psci_stat_residency(uint32_t cpu_id, uint32_t power_state);
 int psci_stat_count(uint32_t cpu_id, uint32_t power_state);
 void tee_psci_handler(struct thread_smc_args *args);
+
+void psci_armv7_cpu_off(void);


Declare also psci_enable/disable_smp(); as they are defined?

They are now only used by psci_armv7_cpu_off. We could export them when we need in future, i think:)

etienne-lms · 2017-06-12T08:47:27Z

core/arch/arm/plat-imx/platform_config.h

@@ -90,14 +90,14 @@
 #endif


-#define CONSOLE_UART_BASE	(UART0_BASE)
+#define CONSOLE_UART_BASE	(UART1_BASE)


minor: useless parenthesis

etienne-lms · 2017-06-12T08:48:34Z

core/arch/arm/plat-imx/imx-regs.h

+
+#define IOMUXC_GPR4_OFFSET	0x10
+#define IOMUXC_GPR5_OFFSET	0x14
+#define ARM_WFI_STAT_MASK(n)	(1 << (n))


minor: BIT(n)

etienne-lms · 2017-06-12T08:52:14Z

core/arch/arm/plat-imx/psci.c

+		"wfi \r\n"
+		"b loop \r\n");
+
+	return PSCI_RET_SUCCESS;


Minor: return value is not reliable.
This should return an error or eventually assert you don't return.

Yeah. needs to return an error value. Thanks.

etienne-lms · 2017-06-12T09:07:02Z

core/arch/arm/plat-imx/psci.c

+	/* Kill cpu */
+	val = read32(va + SRC_SCR);
+	val &= ~BIT32(SRC_SCR_CORE1_ENABLE_OFFSET + (cpu - 1));
+	val |=  BIT32(SRC_SCR_CORE1_RST_OFFSET + (cpu - 1));


minor: useless parenthesis (cpu - 1).

fix in next version.

MrVan · 2017-06-18T11:18:55Z

@etienne-lms Updated with your comments addressed.

etienne-lms · 2017-06-19T08:55:22Z

commit2: "core: arm32_macros: add macros"

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

commit3: "arm: ssvce_a32: introduce cpu_armv7_flush_inner_dcache_all "

See minor comment about inline comments.
This change looks ok but it flushes data to PoC whereas I think one could flush only the L1 cache when used in the psci sequence. Also, on cortex-A5/A9 with a pl310 (or some other external level2 cache), this routine will flush only from the L1 cache, hence not up to the PoC as stated in the comment.
So I think it can be merge as is, and be reviewed once we will merge the 'cache helpers' from Jens (Update cache helpers #1606).

commit4: "core: arm: psci: add helper functions"

please use macro SCTLR_C as suggested in comment.
once fixed: Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

All others commits Acked-by: Etienne Carriere <etienne.carriere@linaro.org> with some few minor comments that can be addressed... or not.

jenswi-linaro · 2017-06-19T09:05:32Z

core/arch/arm/plat-imx/psci.c

+
+	thread_mask_exceptions(THREAD_EXCP_ALL);
+
+	asm volatile(


Why is this preferable over:

while (true) wfi();

@jenswi-linaro if use "while (true)", compiler will complain errors, because this function expects a value returned.

This patch to enable usage of the suggested loop is in my opinion the lesser of two evils.

diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk index 41b4bbcd8b46..e42213caad9f 100644 --- a/core/arch/arm/plat-imx/sub.mk +++ b/core/arch/arm/plat-imx/sub.mk @@ -3,6 +3,7 @@ srcs-y += main.c imx-common.c srcs-$(CFG_PL310) += imx_pl310.c srcs-$(CFG_PSCI_ARM32) += psci.c +cflags-psci.c-y += -Wno-suggest-attribute=noreturn ifneq (,$(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL))) srcs-y += a9_plat_init.S imx6.c

@jenswi-linaro Thanks. fix in next version.

MrVan · 2017-06-19T10:36:10Z

@etienne-lms Thanks. I could follow clearly,"So I think it can be merge as is, and be reviewed once we will merge the 'cache helpers' from Jens (#1606)." you mean this patch needs to be postponed until #1606 merged?

etienne-lms · 2017-06-19T11:14:16Z

(...) you mean this patch needs to be postponed until #1606 merged?

@MrVan, no, rather let's merge your change as you propose them and we will update (if required) when merging #1606. As @jens pointed: "Please go ahead with this PR, waiting for my updates will only delay this."

Note: few of my review comments are still pending, i'll push them...

etienne-lms · 2017-06-19T07:36:35Z

core/arch/arm/kernel/ssvce_a32.S

@@ -125,6 +125,84 @@ UNWIND(	.fnend)
 END_FUNC secure_mmu_unifiedtlbinv_byasid

 /*
+ * From ARM DDI 0406C.c Page B2-1286


Minor generic comment: the code snippet you reference provide few inline comments. Maybe you should preserve them to help understanding the sequence (although the reference you gave is already a good explanation).

ok. I'll add them.

etienne-lms · 2017-06-19T07:41:15Z

core/arch/arm/include/sm/psci.h

@@ -58,3 +58,5 @@ int psci_node_hw_state(uint32_t cpu_id, uint32_t power_level);
 int psci_stat_residency(uint32_t cpu_id, uint32_t power_state);
 int psci_stat_count(uint32_t cpu_id, uint32_t power_state);
 void tee_psci_handler(struct thread_smc_args *args);
+
+void psci_armv7_cpu_off(void);


etienne-lms · 2017-06-19T07:54:44Z

core/arch/arm/plat-imx/a7_plat_init.S

+FUNC plat_cpu_reset_early , :
+UNWIND(	.fnstart)
+
+	mov_imm r0, 0x00000040


Cross-check whether you would not prefer an init value of 0x41 : bit FW of ACTRL enables broadcasting of maintenance operations required for SMP.

minor: would look better using a macro (i.e ACTLR_INIT) from platform_config.h.
Same below with NSACR.

@etienne-lms FW of ACTLR is in A9, not in A7. Let me keep it now, Later I could use a follow up patch to use marco.

etienne-lms · 2017-06-19T08:03:23Z

core/arch/arm/plat-imx/imx6.c

@@ -76,4 +76,3 @@ void plat_cpu_reset_late(void)
 			write32(read32(addr) | CSU_SETTING_LOCK, addr);
 	}
 }


minor: useless change (are better to avoid)

etienne-lms · 2017-06-19T08:05:43Z

core/arch/arm/plat-imx/psci.c

+
+	core_id = get_core_pos();
+
+	write32(~0, va + SRC_GPR1 + core_id * 8 + 4);


this looks redundant with the imx_set_src_gpr(core_id, ~0); implemented below.

Thanks. this needs to be removed.

etienne-lms · 2017-06-19T08:13:33Z

core/arch/arm/plat-imx/psci.c

+	 * Wait secondary cpus ready to be killed
+	 * TODO: Change to non dead loop
+	 */
+	while (read32(va + SRC_GPR1 + cpu * 8 + 4) != (uint32_t)~0)


minor: suggested use of imx_get_src_gpr(cpu).
Can use UINT32_MAX instead of (uint32_t)~0.

etienne-lms · 2017-06-19T08:15:23Z

core/arch/arm/plat-imx/psci.c

+	write32(val, va + SRC_SCR);
+
+	/* Clean arg */
+	write32(0, va + SRC_GPR1 + cpu * 8 + 4);


redundant with the imx_set_src_gpr(cpu, 0); below.

Thanks. Remove.

MrVan · 2017-06-20T05:26:24Z

@etienne-lms @jenswi-linaro Updated

using "while (true) wfi()"
add more comments in the cache flush function according ARM RM
a few minor comments not addressed.
tags applied. only patch "arm: ssvce_a32: introduce cpu_armv7_flush_inner_dcache_all" no review or ack tag.

jenswi-linaro · 2017-06-20T06:17:56Z

core/arch/arm/plat-imx/psci.c

+
+	core_id = get_core_pos();
+
+	DMSG("core_id: %d\n", core_id);


DMSG("core_id: %" PRIu32 , core_id);

Will fix this globally.

jenswi-linaro · 2017-06-20T06:19:22Z

core/arch/arm/plat-imx/psci.c

+{
+	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
+	vaddr_t gpr5 = core_mmu_get_va(IOMUXC_BASE, MEM_AREA_IO_SEC) +
+		IOMUXC_GPR5_OFFSET;


Align this with core_mmu_get_va( at the line above.

linux checkpatch does not report warning on this. To open (, need to align, but here ( is closed with ), no need to align?

Checkpatch is just a tool helping in some situations. You can probably enter the obfuscated C contest with something that checkpatch groks.
Please align it with the start of "core_mmu_get_va" on the line above.

ok. Fix in next version.

jenswi-linaro · 2017-06-20T06:21:00Z

core/arch/arm/plat-imx/psci.c

+	if ((imx_get_src_gpr(cpu) == 0) || !wfi)
+		return PSCI_AFFINITY_LEVEL_ON;
+
+	DMSG("cpu: %d GPR: %x\n", cpu, imx_get_src_gpr(cpu));


DMSG("cpu: %" PRIu32 "GPR: %" PRIx32, cpu, imx_get_src_gpr(cpu));

jenswi-linaro · 2017-06-20T06:22:52Z

core/arch/arm/sm/psci-helper.S

+
+	bl	cpu_armv7_flush_inner_dcache_all
+
+	dsb


cpu_armv7_flush_inner_dcache_all() just finished with:

dsb st isb

Isn't that enough? If an additional dsb is needed please add a comment explaining why.

The isb could be removed. dsb maybe needed, I may need to move it after disable cache and before the second cpu_armv7_flush_inner_dcache_all. dsb is to make all the load/store in order, the last inst of cpu_armv7_flush_inner_dcache_all read from memory and the first inst store to memory.

MrVan · 2017-06-22T03:21:07Z

Updated:
Drop the two patch. @jenswi-linaro introduced related code from ATF.
"core: arm32_macros: add macros"
"arm: ssvce_a32: introduce cpu_armv7_flush_inner_dcache_all "
Addressed comments form @jenswi-linaro

Use "DMSG("core_id: %" PRIu32"
Align code to (

jenswi-linaro · 2017-06-22T06:29:11Z

core/arch/arm/sm/psci-helper.S

+	mov     r0, #DCACHE_OP_CLEAN_INV
+	b	dcache_op_all
+
+	isb


This isb is probably redundant as dcache_op_all() (or do_dcsw_op()) does an isb just before returning.

Will remove it.

jenswi-linaro · 2017-06-22T06:30:17Z

core/arch/arm/sm/psci-helper.S

+	push	{lr}
+
+	mov     r0, #DCACHE_OP_CLEAN_INV
+	b	dcache_op_all


bl dcache_op_all

oh. my bad. pushed wrong patch.

jenswi-linaro · 2017-06-22T06:30:35Z

core/arch/arm/sm/psci-helper.S

+	dsb
+
+	mov	r0, #DCACHE_OP_CLEAN_INV
+	b	dcache_op_all


bl dcache_op_all

jenswi-linaro · 2017-06-22T06:32:36Z

core/arch/arm/sm/psci-helper.S

+
+FUNC psci_armv7_cpu_off, :
+UNWIND(	.fnstart)
+	push	{lr}


When calling other functions it's more safe to keep the stack pointer 8-byte aligned as some function may expect that, it's a requirement in the calling convention.

I did not meet such requirement on i.MX platforms. From "http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042f/IHI0042F_aapcs.pdf" 5.2.1.1 Universal stack constraints: SP mod 4 = 0. The stack must at all times be aligned to a word boundary.

Then there's 5.2.1.2 Stack constraints at a public interface:

The stack must also conform to the following constraint at a public interface:

SP mod 8 = 0. The stack must be double-word aligned.

Ok. Then use "sub sp, sp, #4" after push lr and "add sp, sp, #4" before pop pc. Do you agree with this?

It's less code to just push and pop a dummy register like:

push {r12, lr} pop {r12, pc}

MrVan · 2017-06-23T04:59:34Z

@jenswi-linaro Updated with your comments addressed. Aligned stack to 8 bytes, using "push {r12, lr}" and "pop {r12, pc}", correct "b dcache_op_all" to "bl dcache_op_all", remove the redundant "isb" after dcache_op_all

MrVan · 2017-06-26T00:49:54Z

Is this patchset ok to be merged or any more comments on this patchset? I still have local patches queued to upstream that depends on this patchset.

jenswi-linaro · 2017-06-26T08:36:17Z

Looks good to me:
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

Add helper function psci_armv7_cpu_off. This function will be used when use psci to offline a cpu. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

There is 512M DDR Memory on i.MX6UL-EVK board. Reserve high 32M for TEE usage. The highest 2M for SHMEM. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

Clean up to use one imx-regs.h for i.MX SoC family. If there are different IP address, use CFG_MX6[Q,D,UL] and etc to differentiate them. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

Support psci off and affinity. To i.MX6, CPU could not offline itself, so needs to use core0 to offline other cores. Introduce imx-common.c to include the common code for i.MX family, SRC operation is used by i.MX6/7, so move them to imx-common.c Use CFG_BOOT_SECONDARY_REQUEST to wrap the psci_cpu_on/off/affinity functions, these functions are only needed by SMP systems.To i.MX6UL, they are not needed. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

Switch to use CFG_SECURE_TIME_SOURCE_REE. Since we do not have RTC, and arm counter will lose power when suspend, we use CFG_SECURE_TIME_SOURCE_REE now. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

Add platform early init code. Configure ACTLR to enable SMP. Configure NSACR to let NS could access cp10/cp11 and NS_SMP. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

Add i.MX6 ULL EVK support. i.MX6ULL is derivative from i.MX6UL, so reuse some code for i.MX6UL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

MrVan · 2017-06-26T09:57:35Z

Rebased and Ack tags applied.

MrVan force-pushed the psci-imx branch from 330ed0b to 5390a66 Compare June 2, 2017 11:11

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MrVan force-pushed the psci-imx branch from 5390a66 to 5031785 Compare June 10, 2017 05:03

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MrVan force-pushed the psci-imx branch 2 times, most recently from 03111e0 to 63916d2 Compare June 18, 2017 10:08

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MrVan force-pushed the psci-imx branch from 63916d2 to 66d6898 Compare June 20, 2017 02:23

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MrVan force-pushed the psci-imx branch 2 times, most recently from 0fe8ffa to 5e31729 Compare June 22, 2017 03:18

MrVan force-pushed the psci-imx branch from 5e31729 to 28e6396 Compare June 22, 2017 03:26

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MrVan force-pushed the psci-imx branch from 28e6396 to 8ebf1d6 Compare June 23, 2017 01:20

MrVan added 7 commits June 26, 2017 17:07

core: arm: imx: add 6ULL EVK support

1b9f60e

Add i.MX6 ULL EVK support. i.MX6ULL is derivative from i.MX6UL, so reuse some code for i.MX6UL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

MrVan force-pushed the psci-imx branch from 8ebf1d6 to 1b9f60e Compare June 26, 2017 09:09

jforissier merged commit 796b7a4 into OP-TEE:master Jun 26, 2017

MrVan deleted the psci-imx branch June 26, 2017 12:13


		cpu = affinity;

		wfi = !!(read32(gpr5) & ARM_WFI_STAT_MASK(cpu));


		wfi = !!(read32(gpr5) & ARM_WFI_STAT_MASK(cpu));

		if ((imx_get_src_gpr(cpu) == 0) \|\| !wfi)


		core_id = get_core_pos();

		write32(~0, va + SRC_GPR1 + core_id * 8 + 4);

Add i.MX PSCI CPU off and update i.MX6UL #1577

Add i.MX PSCI CPU off and update i.MX6UL #1577

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MrVan commented Jun 2, 2017

MrVan commented Jun 2, 2017

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etienne-lms Jun 2, 2017 • edited Loading

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jenswi-linaro commented Jun 7, 2017

MrVan commented Jun 7, 2017

MrVan commented Jun 8, 2017

jenswi-linaro commented Jun 8, 2017

MrVan commented Jun 10, 2017

jforissier commented Jun 12, 2017

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MrVan commented Jun 18, 2017

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MrVan commented Jun 19, 2017

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MrVan commented Jun 20, 2017

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etienne-lms left a comment •

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etienne-lms Jun 2, 2017 •

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