hikey960: Initial commit

.travis.yml

@@ -180,6 +180,11 @@ script:
   - $make PLATFORM=hikey
   - $make PLATFORM=hikey CFG_ARM64_core=y
   - $make PLATFORM=hikey CFG_ARM64_core=y CFG_TEE_TA_LOG_LEVEL=4 DEBUG=1
+  #
+  # HiKey960 board (HiSilicon Kirin 960)
+  - $make PLATFORM=hikey960
+  - $make PLATFORM=hikey960 CFG_ARM64_core=y
+  - $make PLATFORM=hikey960 CFG_ARM64_core=y CFG_TEE_TA_LOG_LEVEL=4 DEBUG=1
 
   # Mediatek mt8173 EVB
   - $make PLATFORM=mediatek-mt8173 CFG_ARM64_core=y

MAINTAINERS.md

@@ -17,6 +17,7 @@ for these platforms.
 | NXP i.MX7 Dual SabreSD Board		|`Peng Fan <peng.fan@nxp.com>`|
 | ARM Foundation FVP			|`Linaro <op-tee@linaro.org>`|
 | HiKey Board (HiSilicon Kirin 620)	|`Linaro <op-tee@linaro.org>`|
+| HiKey960 Board (HiSilicon Kirin 960)	|`Linaro <op-tee@linaro.org>`|
 | HiSilicon D02				|`Linaro <op-tee@linaro.org>`|
 | MediaTek MT8173 EVB Board		|`Linaro <op-tee@linaro.org>`|
 | QEMU					|`Linaro <op-tee@linaro.org>`|

README.md

@@ -54,6 +54,7 @@ platforms have different sub-maintainers, please refer to the file
 | [ARM Foundation FVP](https://developer.arm.com/products/system-design/fixed-virtual-platforms) |`PLATFORM=vexpress-fvp`| Yes |
 | [HiSilicon D02](http://open-estuary.org/d02-2)|`PLATFORM=d02`| No |
 | [HiKey Board (HiSilicon Kirin 620)](https://www.96boards.org/products/hikey)|`PLATFORM=hikey`| Yes |
+| [HiKey960 Board (HiSilicon Kirin 960)](https://www.96boards.org/products/hikey960)|`PLATFORM=hikey960`| Yes |
 | [MediaTek MT8173 EVB Board](https://www.mediatek.com/products/tablets/mt8173)|`PLATFORM=mediatek-mt8173`| No |
 | [QEMU](http://wiki.qemu.org/Main_Page) |`PLATFORM=vexpress-qemu_virt`| Yes |
 | [QEMUv8](http://wiki.qemu.org/Main_Page) |`PLATFORM=vexpress-qemu_armv8a`| Yes |

core/arch/arm/plat-hikey960/conf.mk

@@ -0,0 +1,27 @@
+include core/arch/arm/cpu/cortex-armv8-0.mk
+
+# 32-bit flags
+core_arm32-platform-aflags	+= -mfpu=neon
+
+$(call force,CFG_GENERIC_BOOT,y)
+$(call force,CFG_PL011,y)
+$(call force,CFG_PM_STUBS,y)
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
+
+ta-targets = ta_arm32
+
+ifeq ($(CFG_ARM64_core),y)
+$(call force,CFG_WITH_LPAE,y)
+ta-targets += ta_arm64
+else
+$(call force,CFG_ARM32_core,y)
+endif
+
+CFG_NUM_THREADS ?= 8
+CFG_CRYPTO_WITH_CE ?= y
+CFG_WITH_STACK_CANARIES ?= y
+
+CFG_SECURE_DATA_PATH ?= y
+CFG_TEE_SDP_MEM_BASE ?= 0x3E800000
+CFG_TEE_SDP_MEM_SIZE ?= 0x00400000

core/arch/arm/plat-hikey960/kern.ld.S

@@ -0,0 +1 @@
+#include "../kernel/kern.ld.S"

core/arch/arm/plat-hikey960/link.mk

@@ -0,0 +1 @@
+include core/arch/arm/kernel/link.mk

core/arch/arm/plat-hikey960/main.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2017, Linaro Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <console.h>
+#include <drivers/pl011.h>
+#include <kernel/generic_boot.h>
+#include <kernel/panic.h>
+#include <kernel/pm_stubs.h>
+#include <mm/core_memprot.h>
+#include <mm/tee_pager.h>
+#include <platform_config.h>
+#include <stdint.h>
+#include <tee/entry_std.h>
+#include <tee/entry_fast.h>
+
+static void main_fiq(void);
+
+static const struct thread_handlers handlers = {
+	.std_smc = tee_entry_std,
+	.fast_smc = tee_entry_fast,
+	.nintr = main_fiq,
+	.cpu_on = cpu_on_handler,
+	.cpu_off = pm_do_nothing,
+	.cpu_suspend = pm_do_nothing,
+	.cpu_resume = pm_do_nothing,
+	.system_off = pm_do_nothing,
+	.system_reset = pm_do_nothing,
+};
+
+static struct pl011_data console_data;
+
+register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
+
+const struct thread_handlers *generic_boot_get_handlers(void)
+{
+	return &handlers;
+}
+
+static void main_fiq(void)
+{
+	panic();
+}
+
+void console_init(void)
+{
+	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
+		   CONSOLE_BAUDRATE);
+	register_serial_console(&console_data.chip);
+}

core/arch/arm/plat-hikey960/platform_config.h

@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2017, Linaro Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PLATFORM_CONFIG_H
+#define PLATFORM_CONFIG_H
+
+/* Make stacks aligned to data cache line length */
+#define STACK_ALIGNMENT		64
+
+/* PL011 UART */
+#define PL011_UART5_BASE		0xFDF05000
+#define PL011_UART6_BASE		0xFFF32000
+
+#if defined(CFG_CONSOLE_UART) && (CFG_CONSOLE_UART == 5)
+#define CONSOLE_UART_BASE       PL011_UART5_BASE
+#elif !defined(CFG_CONSOLE_UART) || (CFG_CONSOLE_UART == 6)
+#define CONSOLE_UART_BASE       PL011_UART6_BASE
+#else
+#error Unknown console UART
+#endif
+
+#define CONSOLE_BAUDRATE		115200
+#define CONSOLE_UART_CLK_IN_HZ	19200000
+
+/*
+ * HiKey960 memory map
+ *
+ * TZDRAM is secured (firewalled) by the DDR controller, see ARM-TF, but note
+ * that security of this type of memory is weak for two reasons:
+ *   1. It is prone to physical tampering since DRAM is external to the SoC
+ *   2. It is still somewhat prone to software attacks because the memory
+ *      protection may be reverted by the non-secure kernel with a piece of
+ *      code similar to the one that sets the protection in ARM-TF (we're
+ *      missing a "lockdown" step which would prevent any change to the DDRC
+ *      configuration until the next SoC reset).
+ * TZSRAM is emulated in the TZDRAM area, because the on-chip SRAM of the SoC
+ * is not available to the public at the moment.
+ *
+ * CFG_WITH_PAGER=n
+ *
+ *  0x4000_0000                               -
+ *    TA RAM: 15 MiB                          |
+ *  0x3F10_0000                               | TZDRAM
+ *    TEE RAM: 1 MiB (CFG_TEE_RAM_VA_SIZE)    |
+ *  0x3F00_0000 [TZDRAM_BASE, BL32_LOAD_ADDR] -
+ *    Shared memory: 2 MiB                    |
+ *  0x3EE0_0000                               | DRAM0
+ *    Reserved by UEFI for OP-TEE, unused     |
+ *  0x3EC0_0000                               -
+ *    Secure Data Path buffers: 4 MiB         | DRAM0 (secure)
+ *  0x3E80_0000 [CFG_TEE_SDP_MEM_BASE]        -
+ *    Reserved by UEFI for OP-TEE, unused     |
+ *  0x3E00_0000                               | DRAM0
+ *    Available to Linux                      |
+ *  0x0000_0000 [DRAM0_BASE]                  -
+ *
+ * CFG_WITH_PAGER=y
+ *
+ *  0x4000_0000                               -
+ *    TA RAM: 15 MiB                          | TZDRAM
+ *  0x3F10_0000                               -
+ *    Unused
+ *  0x3F03_2000                               -
+ *    TEE RAM: 200 KiB                        | TZSRAM
+ *  0x3F00_0000 [TZSRAM_BASE, BL32_LOAD_ADDR] -
+ *    Shared memory: 2 MiB                    |
+ *  0x3EE0_0000                               | DRAM0
+ *    Reserved by UEFI for OP-TEE, unused     |
+ *  0x3EC0_0000                               -
+ *    Secure Data Path buffers: 4 MiB         | DRAM0 (secure)
+ *  0x3E80_0000 [CFG_TEE_SDP_MEM_BASE]        -
+ *    Reserved by UEFI for OP-TEE, unused     |
+ *  0x3E00_0000                               | DRAM0
+ *    Available to Linux                      |
+ *  0x0000_0000 [DRAM0_BASE]                  -
+ */
+
+#define DRAM0_BASE		0x00000000
+#define DRAM0_SIZE		0x3F000000
+
+#ifdef CFG_WITH_PAGER
+
+#define TZSRAM_BASE		0x3F000000
+#define TZSRAM_SIZE		CFG_CORE_TZSRAM_EMUL_SIZE
+
+#define TZDRAM_BASE		0x3F100000
+#define TZDRAM_SIZE		(15 * 1024 * 1024)
+
+#else /* CFG_WITH_PAGER */
+
+#define TZDRAM_BASE		0x3F000000
+#define TZDRAM_SIZE		(16 * 1024 * 1024)
+
+#endif /* CFG_WITH_PAGER */
+
+#define CFG_SHMEM_START		0x3EE00000
+#define CFG_SHMEM_SIZE		(2 * 1024 * 1024)
+
+#define CFG_TEE_CORE_NB_CORE	8
+
+#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+
+#define CFG_TEE_LOAD_ADDR	0x3F000000
+
+#ifdef CFG_WITH_PAGER
+
+#define CFG_TEE_RAM_START	TZSRAM_BASE
+#define CFG_TEE_RAM_PH_SIZE	TZSRAM_SIZE
+#define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE)
+#define CFG_TA_RAM_SIZE		ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE)
+
+#else /* CFG_WITH_PAGER */
+
+#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
+#define CFG_TEE_RAM_START	TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+					CORE_MMU_DEVICE_SIZE)
+
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE),\
+					  CORE_MMU_DEVICE_SIZE)
+
+#endif /* CFG_WITH_PAGER */
+
+#endif /* PLATFORM_CONFIG_H */

core/arch/arm/plat-hikey960/sub.mk

@@ -0,0 +1,2 @@
+global-incdirs-y += .
+srcs-y += main.c