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1. caution: If you have used ASYNCHRONOUS "clear" signal, to clear registers in the testbench, there are 2 solutions:

Solution 1: use the "transition" of "clear" signal to clear registers.
Solution 2: Set "clear" signal to 0 and wait for a positive-edge clock to trigger the clear operation.
I think solution 1 is better than solution 2.

    always @(posedge clk, negedge clear_low) begin
        if (1'b0 == clear_low)
            Q <= 4'b0;
        else if(1'b1 == shift_control) 
            Q <= {serial_input, Q[3:1]};
    end

In the testbench

   initial fork
      /*
      {clear_A, clear_B, clear_FF} = 3'b0;
      #26 {clear_A, clear_B, clear_FF} = 3'b111;
      */

      {clear_A, clear_B, clear_FF} = 3'b111;
      #3 {clear_A, clear_B, clear_FF} = 3'b000;
      #26 {clear_A, clear_B, clear_FF} = 3'b111;
  join

2. Caution: asynchronous clocks are very dangerous

Problem: chapter 6, Problem 6.35 (h)(i). When I implement the two serial adders in Figure 6.5(page 278) and Figure 6.6(page 280), I found that if you change "shift control" signal arbitrarily in the testbench, the shift registers and flip flop may have ASYNCHRONOUS clocks. Before the next positive-edge of the clock to the shift registers, if the positive-edge of the clock to the flip flop occurs, then the serial input to shift register A may change, thus it cause an error as the following shows.
Solution: make sure the clock signals to shift registers and flip flop are the same