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rv64v: fix some code style for vector instructions
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* use vp_set_dirty instead of set_mstatus_dirt
* fix vfredusom calculation
* add more comments
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@Ziyue-Zhang
Ziyue-Zhang committed Jan 24, 2024
1 parent b4f87c7 commit a4dd9c0
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Showing 17 changed files with 166 additions and 119 deletions.
2 changes: 1 addition & 1 deletion include/cpu/decode.h
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Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ typedef struct Decode {
int v_width;
int v_nf;
int v_lsumop;
int v_is_vx;
int v_is_vx; // 1: vector indexed load/store instruction; 0: other vector load/store instruction
uint32_t vm;
uint32_t src_vmode;
rtlreg_t tmp_reg[4];
Expand Down
2 changes: 1 addition & 1 deletion include/rtl/fp.h
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Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,7 @@ enum {
FPCALL_DUToF,
FPCALL_DSToF,
FPCALL_DFToF,
FPCALL_DFToFR
FPCALL_DFToF_ODD, // round odd
};

#define FPCALL_CMD(op, w) (((op) << 16) | (w))
Expand Down
4 changes: 2 additions & 2 deletions src/engine/interpreter/fp.c
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Original file line number Diff line number Diff line change
Expand Up @@ -296,7 +296,7 @@ def_rtl(vfpcall, rtlreg_t *dest, const rtlreg_t *src1, const rtlreg_t *src2, uin
case FPCALL_DUToF: *dest = ui32_to_f16(fsrc1.v).v; break;
case FPCALL_DSToF: *dest = i32_to_f16(fsrc1.v).v; break;
case FPCALL_DFToF: *dest = f32_to_f16(fsrc1).v; break;
case FPCALL_DFToFR:
case FPCALL_DFToF_ODD:
softfloat_roundingMode = softfloat_round_odd;
*dest = f32_to_f16(fsrc1).v;
break;
Expand Down Expand Up @@ -373,7 +373,7 @@ def_rtl(vfpcall, rtlreg_t *dest, const rtlreg_t *src1, const rtlreg_t *src2, uin
case FPCALL_DUToF: *dest = ui64_to_f32(fsrc1.v).v; break;
case FPCALL_DSToF: *dest = i64_to_f32(fsrc1.v).v; break;
case FPCALL_DFToF: *dest = f64_to_f32(fsrc1).v; break;
case FPCALL_DFToFR:
case FPCALL_DFToF_ODD:
softfloat_roundingMode = softfloat_round_odd;
*dest = f64_to_f32(fsrc1).v;
break;
Expand Down
8 changes: 4 additions & 4 deletions src/isa/riscv64/include/isa-def.h
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Original file line number Diff line number Diff line change
Expand Up @@ -217,25 +217,25 @@ typedef struct {
uint32_t v_vs2 : 5;
uint32_t v_vm : 1;
uint32_t v_funct6 : 6;
} v_opv1;
} v_opv;
struct {
uint32_t pad0 :15;
int32_t v_simm5 : 5;
uint32_t v_zimm :11;
uint32_t v_bigbit : 1;
} v_opv2;
} v_opsimm;
struct {
uint32_t pad0 :15;
uint32_t v_imm5 : 5;
uint32_t v_zimm :11;
uint32_t v_bigbit : 1;
} v_opv3;
} v_opimm;
struct {
uint32_t pad0 :15;
uint32_t v_zimm5 : 5;
uint32_t v_zimm :10;
uint32_t v_bigbit : 2;
} v_opv4;
} v_vseti;
//vector-LOAD-FP
struct {
uint32_t pad0 :12;
Expand Down
52 changes: 26 additions & 26 deletions src/isa/riscv64/instr/rvf/decode.h
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Original file line number Diff line number Diff line change
Expand Up @@ -67,46 +67,46 @@ static inline def_DHelper(r2fr){
#ifdef CONFIG_RVV
bool vp_enable();
def_THelper(vload) {
def_INSTR_TAB("??? 000 ? ?0000 ????? ??? ????? ????? ??", vle);
def_INSTR_TAB("??? 000 ? 01000 ????? ??? ????? ????? ??", vlr);
def_INSTR_TAB("??? 000 ? 01011 ????? ??? ????? ????? ??", vlm);
def_INSTR_TAB("??? 001 ? ????? ????? ??? ????? ????? ??", vlxe);
def_INSTR_TAB("??? 010 ? ????? ????? ??? ????? ????? ??", vlse);
def_INSTR_TAB("??? 011 ? ????? ????? ??? ????? ????? ??", vlxe);
def_INSTR_TAB("??? 000 ? ?0000 ????? ??? ????? ????? ??", vle); // VLE
def_INSTR_TAB("??? 000 ? 01000 ????? ??? ????? ????? ??", vlr); // VLR
def_INSTR_TAB("??? 000 ? 01011 ????? ??? ????? ????? ??", vlm); // VLM
def_INSTR_TAB("??? 001 ? ????? ????? ??? ????? ????? ??", vlxe); // VLUXEI
def_INSTR_TAB("??? 010 ? ????? ????? ??? ????? ????? ??", vlse); // VLSE
def_INSTR_TAB("??? 011 ? ????? ????? ??? ????? ????? ??", vlxe); // VLOXEI
return EXEC_ID_inv;
}

def_THelper(vstore) {
decode_op_i(s, id_src2, (sword_t)s->isa.instr.i.simm11_0, false);
decode_op_fr(s, id_dest, s->isa.instr.i.rd, false);
def_INSTR_TAB("??? 000 ? 00000 ????? ??? ????? ????? ??", vse);
def_INSTR_TAB("??? 000 ? 01000 ????? ??? ????? ????? ??", vsr);
def_INSTR_TAB("??? 000 ? 01011 ????? ??? ????? ????? ??", vsm);
def_INSTR_TAB("??? 001 ? ????? ????? ??? ????? ????? ??", vsxe);
def_INSTR_TAB("??? 010 ? ????? ????? ??? ????? ????? ??", vsse);
def_INSTR_TAB("??? 011 ? ????? ????? ??? ????? ????? ??", vsxe);
def_INSTR_TAB("??? 000 ? 00000 ????? ??? ????? ????? ??", vse); // VSE
def_INSTR_TAB("??? 000 ? 01000 ????? ??? ????? ????? ??", vsr); // VSR
def_INSTR_TAB("??? 000 ? 01011 ????? ??? ????? ????? ??", vsm); // VSM
def_INSTR_TAB("??? 001 ? ????? ????? ??? ????? ????? ??", vsxe); // VSUXEI
def_INSTR_TAB("??? 010 ? ????? ????? ??? ????? ????? ??", vsse); // VSSE
def_INSTR_TAB("??? 011 ? ????? ????? ??? ????? ????? ??", vsxe); // VSOXEI
return EXEC_ID_inv;
}

def_THelper(vload_mmu) {
def_INSTR_TAB("??? 000 ? ?0000 ????? ??? ????? ????? ??", vle_mmu);
def_INSTR_TAB("??? 000 ? 01000 ????? ??? ????? ????? ??", vlr_mmu);
def_INSTR_TAB("??? 000 ? 01011 ????? ??? ????? ????? ??", vlm_mmu);
def_INSTR_TAB("??? 001 ? ????? ????? ??? ????? ????? ??", vlxe_mmu);
def_INSTR_TAB("??? 010 ? ????? ????? ??? ????? ????? ??", vlse_mmu);
def_INSTR_TAB("??? 011 ? ????? ????? ??? ????? ????? ??", vlxe_mmu);
def_INSTR_TAB("??? 000 ? ?0000 ????? ??? ????? ????? ??", vle_mmu); // VLE
def_INSTR_TAB("??? 000 ? 01000 ????? ??? ????? ????? ??", vlr_mmu); // VLR
def_INSTR_TAB("??? 000 ? 01011 ????? ??? ????? ????? ??", vlm_mmu); // VLM
def_INSTR_TAB("??? 001 ? ????? ????? ??? ????? ????? ??", vlxe_mmu); // VLUXEI
def_INSTR_TAB("??? 010 ? ????? ????? ??? ????? ????? ??", vlse_mmu); // VLSE
def_INSTR_TAB("??? 011 ? ????? ????? ??? ????? ????? ??", vlxe_mmu); // VLOXEI
return EXEC_ID_inv;
}

def_THelper(vstore_mmu) {
decode_op_i(s, id_src2, (sword_t)s->isa.instr.i.simm11_0, false);
decode_op_fr(s, id_dest, s->isa.instr.i.rd, false);
def_INSTR_TAB("??? 000 ? 00000 ????? ??? ????? ????? ??", vse_mmu);
def_INSTR_TAB("??? 000 ? 01000 ????? ??? ????? ????? ??", vsr_mmu);
def_INSTR_TAB("??? 000 ? 01011 ????? ??? ????? ????? ??", vsm_mmu);
def_INSTR_TAB("??? 001 ? ????? ????? ??? ????? ????? ??", vsxe_mmu);
def_INSTR_TAB("??? 010 ? ????? ????? ??? ????? ????? ??", vsse_mmu);
def_INSTR_TAB("??? 011 ? ????? ????? ??? ????? ????? ??", vsxe_mmu);
def_INSTR_TAB("??? 000 ? 00000 ????? ??? ????? ????? ??", vse_mmu); // VSE
def_INSTR_TAB("??? 000 ? 01000 ????? ??? ????? ????? ??", vsr_mmu); // VSR
def_INSTR_TAB("??? 000 ? 01011 ????? ??? ????? ????? ??", vsm_mmu); // VSM
def_INSTR_TAB("??? 001 ? ????? ????? ??? ????? ????? ??", vsxe_mmu); // VSUXEI
def_INSTR_TAB("??? 010 ? ????? ????? ??? ????? ????? ??", vsse_mmu); // VSSE
def_INSTR_TAB("??? 011 ? ????? ????? ??? ????? ????? ??", vsxe_mmu); // VSOXEI
return EXEC_ID_inv;
}

Expand All @@ -117,7 +117,7 @@ def_THelper(fload) {

#ifdef CONFIG_RVV
const int table [8] = {1, 0, 0, 0, 0, 2, 4, 8};
s->vm = s->isa.instr.v_opv1.v_vm; //1 for without mask; 0 for with mask
s->vm = s->isa.instr.v_opv.v_vm; //1 for without mask; 0 for with mask
s->v_width = table[s->isa.instr.vldfp.v_width];
s->v_nf = s->isa.instr.vldfp.v_nf;
s->v_lsumop = s->isa.instr.vldfp.v_lsumop;
Expand Down Expand Up @@ -165,7 +165,7 @@ def_THelper(fstore) {

#ifdef CONFIG_RVV
const int table [8] = {1, 0, 0, 0, 0, 2, 4, 8};
s->vm = s->isa.instr.v_opv1.v_vm; //1 for without mask; 0 for with mask
s->vm = s->isa.instr.v_opv.v_vm; //1 for without mask; 0 for with mask
s->v_width = table[s->isa.instr.vldfp.v_width];
s->v_nf = s->isa.instr.vldfp.v_nf;
s->v_lsumop = s->isa.instr.vldfp.v_lsumop;
Expand Down
90 changes: 78 additions & 12 deletions src/isa/riscv64/instr/rvv/decode.h
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Original file line number Diff line number Diff line change
Expand Up @@ -24,11 +24,16 @@ static inline def_DHelper(OP_V) { // 10_101, same to R
decode_op_r(s, id_dest, s->isa.instr.r.rd, false);
}

def_THelper(vrwxunary0_dispatch) {
def_INSTR_TAB("?????? ? 00000 ????? 110 ????? ????? ??", vmvsx);
def_INSTR_TAB("?????? ? ????? 00000 010 ????? ????? ??", vmvxs);
def_INSTR_TAB("?????? ? ????? 10000 010 ????? ????? ??", vpopc);
def_INSTR_TAB("?????? ? ????? 10001 010 ????? ????? ??", vfirst);
def_THelper(vwxunary0_dispatch) {
def_INSTR_TAB("?????? ? ????? 00000 ??? ????? ????? ??", vmvxs);
def_INSTR_TAB("?????? ? ????? 10000 ??? ????? ????? ??", vpopc);
def_INSTR_TAB("?????? ? ????? 10001 ??? ????? ????? ??", vfirst);

return EXEC_ID_inv;
}

def_THelper(vrxunary0_dispatch) {
def_INSTR_TAB("?????? ? 00000 ????? ??? ????? ????? ??", vmvsx);

return EXEC_ID_inv;
}
Expand Down Expand Up @@ -277,7 +282,7 @@ def_THelper(vopivi) {
//longjmp_raise_intr(EX_II);
}

def_THelper(vopm) {
def_THelper(vopmvv) {
if (!vp_enable()) {
return EXEC_ID_inv;
}
Expand All @@ -297,9 +302,70 @@ def_THelper(vopm) {
def_INSTR_TAB("001110 ? ????? ????? ??? ????? ????? ??", vslide1up);
def_INSTR_TAB("001111 ? ????? ????? ??? ????? ????? ??", vslide1down);

def_INSTR_TAB("010000 ? ????? ????? ??? ????? ????? ??", vrwxunary0_dispatch);
def_INSTR_TAB("010010 ? ????? ????? 010 ????? ????? ??", vxunary0_dispatch);
def_INSTR_TAB("010100 ? ????? ????? 010 ????? ????? ??", vmunary0_dispatch);
def_INSTR_TAB("010000 ? ????? ????? ??? ????? ????? ??", vwxunary0_dispatch);
def_INSTR_TAB("010010 ? ????? ????? ??? ????? ????? ??", vxunary0_dispatch);
def_INSTR_TAB("010100 ? ????? ????? ??? ????? ????? ??", vmunary0_dispatch);
def_INSTR_TAB("010111 ? ????? ????? ??? ????? ????? ??", vcompress);
def_INSTR_TAB("011000 ? ????? ????? ??? ????? ????? ??", vmandnot);
def_INSTR_TAB("011001 ? ????? ????? ??? ????? ????? ??", vmand);
def_INSTR_TAB("011010 ? ????? ????? ??? ????? ????? ??", vmor);
def_INSTR_TAB("011011 ? ????? ????? ??? ????? ????? ??", vmxor);
def_INSTR_TAB("011100 ? ????? ????? ??? ????? ????? ??", vmornot);
def_INSTR_TAB("011101 ? ????? ????? ??? ????? ????? ??", vmnand);
def_INSTR_TAB("011110 ? ????? ????? ??? ????? ????? ??", vmnor);
def_INSTR_TAB("011111 ? ????? ????? ??? ????? ????? ??", vmxnor);
def_INSTR_TAB("100000 ? ????? ????? ??? ????? ????? ??", vdivu);
def_INSTR_TAB("100001 ? ????? ????? ??? ????? ????? ??", vdiv);
def_INSTR_TAB("100010 ? ????? ????? ??? ????? ????? ??", vremu);
def_INSTR_TAB("100011 ? ????? ????? ??? ????? ????? ??", vrem);
def_INSTR_TAB("100100 ? ????? ????? ??? ????? ????? ??", vmulhu);
def_INSTR_TAB("100101 ? ????? ????? ??? ????? ????? ??", vmul);
def_INSTR_TAB("100110 ? ????? ????? ??? ????? ????? ??", vmulhsu);
def_INSTR_TAB("100111 ? ????? ????? ??? ????? ????? ??", vmulh);
def_INSTR_TAB("101001 ? ????? ????? ??? ????? ????? ??", vmadd);
def_INSTR_TAB("101011 ? ????? ????? ??? ????? ????? ??", vnmsub);
def_INSTR_TAB("101101 ? ????? ????? ??? ????? ????? ??", vmacc);
def_INSTR_TAB("101111 ? ????? ????? ??? ????? ????? ??", vnmsac);
def_INSTR_TAB("110000 ? ????? ????? ??? ????? ????? ??", vwaddu);
def_INSTR_TAB("110001 ? ????? ????? ??? ????? ????? ??", vwadd);
def_INSTR_TAB("110010 ? ????? ????? ??? ????? ????? ??", vwsubu);
def_INSTR_TAB("110011 ? ????? ????? ??? ????? ????? ??", vwsub);
def_INSTR_TAB("110100 ? ????? ????? ??? ????? ????? ??", vwaddu_w);
def_INSTR_TAB("110101 ? ????? ????? ??? ????? ????? ??", vwadd_w);
def_INSTR_TAB("110110 ? ????? ????? ??? ????? ????? ??", vwsubu_w);
def_INSTR_TAB("110111 ? ????? ????? ??? ????? ????? ??", vwsub_w);
def_INSTR_TAB("111000 ? ????? ????? ??? ????? ????? ??", vwmulu);
def_INSTR_TAB("111010 ? ????? ????? ??? ????? ????? ??", vwmulsu);
def_INSTR_TAB("111011 ? ????? ????? ??? ????? ????? ??", vwmul);
def_INSTR_TAB("111100 ? ????? ????? ??? ????? ????? ??", vwmaccu);
def_INSTR_TAB("111101 ? ????? ????? ??? ????? ????? ??", vwmacc);
def_INSTR_TAB("111110 ? ????? ????? ??? ????? ????? ??", vwmaccus);
def_INSTR_TAB("111111 ? ????? ????? ??? ????? ????? ??", vwmaccsu);

return EXEC_ID_inv;
}

def_THelper(vopmvx) {
if (!vp_enable()) {
return EXEC_ID_inv;
}
def_INSTR_TAB("000000 ? ????? ????? ??? ????? ????? ??", vredsum);
def_INSTR_TAB("000001 ? ????? ????? ??? ????? ????? ??", vredand);
def_INSTR_TAB("000010 ? ????? ????? ??? ????? ????? ??", vredor);
def_INSTR_TAB("000011 ? ????? ????? ??? ????? ????? ??", vredxor);
def_INSTR_TAB("000100 ? ????? ????? ??? ????? ????? ??", vredminu);
def_INSTR_TAB("000101 ? ????? ????? ??? ????? ????? ??", vredmin);
def_INSTR_TAB("000110 ? ????? ????? ??? ????? ????? ??", vredmaxu);
def_INSTR_TAB("000111 ? ????? ????? ??? ????? ????? ??", vredmax);
def_INSTR_TAB("001000 ? ????? ????? ??? ????? ????? ??", vaaddu);
def_INSTR_TAB("001001 ? ????? ????? ??? ????? ????? ??", vaadd);
def_INSTR_TAB("001010 ? ????? ????? ??? ????? ????? ??", vasubu);
def_INSTR_TAB("001011 ? ????? ????? ??? ????? ????? ??", vasub);

def_INSTR_TAB("001110 ? ????? ????? ??? ????? ????? ??", vslide1up);
def_INSTR_TAB("001111 ? ????? ????? ??? ????? ????? ??", vslide1down);

def_INSTR_TAB("010000 ? ????? ????? ??? ????? ????? ??", vrxunary0_dispatch);
def_INSTR_TAB("010111 ? ????? ????? ??? ????? ????? ??", vcompress);
def_INSTR_TAB("011000 ? ????? ????? ??? ????? ????? ??", vmandnot);
def_INSTR_TAB("011001 ? ????? ????? ??? ????? ????? ??", vmand);
Expand Down Expand Up @@ -455,7 +521,7 @@ def_THelper(OP_V) { // 10_101
}

s->v_width = 1 << vtype->vsew;
s->vm = s->isa.instr.v_opv1.v_vm; //1 for without mask; 0 for with mask
s->vm = s->isa.instr.v_opv.v_vm; //1 for without mask; 0 for with mask

/*
switch(s->isa.instr.i.funct3) {
Expand All @@ -464,11 +530,11 @@ def_THelper(OP_V) { // 10_101
*/
def_INSTR_TAB("??????? ????? ????? 000 ????? ????? ??", vopivv);
def_INSTR_TAB("??????? ????? ????? 001 ????? ????? ??", vopfvv);
def_INSTR_TAB("??????? ????? ????? 010 ????? ????? ??", vopm);
def_INSTR_TAB("??????? ????? ????? 010 ????? ????? ??", vopmvv);
def_INSTR_TAB("??????? ????? ????? 011 ????? ????? ??", vopivi);
def_INSTR_TAB("??????? ????? ????? 100 ????? ????? ??", vopivx);
def_INSTR_TAB("??????? ????? ????? 101 ????? ????? ??", vopfvf);
def_INSTR_TAB("??????? ????? ????? 110 ????? ????? ??", vopm);
def_INSTR_TAB("??????? ????? ????? 110 ????? ????? ??", vopmvx);
def_INSTR_TAB("??????? ????? ????? 111 ????? ????? ??", vsetvl_dispatch);
return EXEC_ID_inv;
}
Expand Down
20 changes: 11 additions & 9 deletions src/isa/riscv64/instr/rvv/vcfg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,11 @@
#include "vcommon.h"

int get_mode(Decode *s) {
/*
* mode 0: rs1 != 0, Normal stripmining
* mode 1: rd != 0, rs1 == 0, Set vl to VLMAX
* mode 2: rd == 0, rs1 == 0, Keep existing vl
*/
int mode = 0;
if (id_src1->reg == 0 && id_dest->reg != 0) {
mode = 1;
Expand Down Expand Up @@ -69,30 +74,27 @@ def_EHelper(vsetvl) {
rtl_lr(s, &(s->src2.val), s->src2.reg, 4);
int mode = get_mode(s);
set_vtype_vl(s, mode);
set_mstatus_dirt();
// print_asm_template3(vsetvl);
vp_set_dirty();
}

def_EHelper(vsetvli) {

//vlmul+lg2(VLEN) <= vsew + vl
// previous decode does not load vals for us
rtl_lr(s, &(s->src1.val), s->src1.reg, 4);
rtl_li(s, &(s->src2.val), s->isa.instr.v_opv2.v_zimm);
rtl_li(s, &(s->src2.val), s->isa.instr.v_opsimm.v_zimm);
int mode = get_mode(s);
set_vtype_vl(s, mode);
set_mstatus_dirt();
// print_asm_template3(vsetvl);
vp_set_dirty();
}

def_EHelper(vsetivli) {
//vlmul+lg2(VLEN) <= vsew + vl
// previous decode does not load vals for us
rtl_li(s, &(s->src1.val), s->isa.instr.v_opv4.v_zimm5);
rtl_li(s, &(s->src2.val), s->isa.instr.v_opv4.v_zimm);
rtl_li(s, &(s->src1.val), s->isa.instr.v_vseti.v_zimm5);
rtl_li(s, &(s->src2.val), s->isa.instr.v_vseti.v_zimm);
set_vtype_vl(s, 0);
set_mstatus_dirt();
// print_asm_template3(vsetvl);
vp_set_dirty();
}

#endif // CONFIG_RVV
3 changes: 1 addition & 2 deletions src/isa/riscv64/instr/rvv/vcommon.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,11 +5,10 @@
#include "vcommon.h"
uint8_t check_vstart_ignore(Decode *s) {
if(vstart->val >= vl->val) {
// Log("vstart=%lu vl=%lu", vstart->val, vl->val);
if(vstart->val > 0) {
rtl_li(s, s0, 0);
vcsr_write(IDXVSTART, s0);
set_mstatus_dirt();
vp_set_dirty();
}
return 1;
}
Expand Down
1 change: 1 addition & 0 deletions src/isa/riscv64/instr/rvv/vcommon.h
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@

uint8_t check_vstart_ignore(Decode *s);
bool check_vlmul_sew_illegal(rtlreg_t vtype_req);
void vp_set_dirty();

#endif
#endif
9 changes: 6 additions & 3 deletions src/isa/riscv64/instr/rvv/vcompute.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -348,7 +348,7 @@ def_EHelper(vmvxs) {
}

def_EHelper(vmvnr) {
rtl_li(s, s1, s->isa.instr.v_opv3.v_imm5);
rtl_li(s, s1, s->isa.instr.v_opimm.v_imm5);
int NREG = (*s1) + 1;
int len = (VLEN >> 6) * NREG;
int vlmul = 0;
Expand Down Expand Up @@ -838,8 +838,11 @@ def_EHelper(vfadd) {
}

def_EHelper(vfredusum) {
FREDUCTION(FREDUSUM)
//float_reduction_computing(s);
#ifdef CONFIG_DIFFTEST
FREDUCTION(FREDUSUM) // use ordered reduction
#else
float_reduction_computing(s); // when NEMU is ref, use unordered reduction which is same as XiangShan
#endif
}

def_EHelper(vfsub) {
Expand Down
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