feat(PMA, CSR): support PMA Custom CSR configurable

* We implements 16 PMA entries, all PMA CSR fields are WARL
  and may be read-only zero.

* That means that accessing CSRs of implemented PMA entries
  should not rasie illegal instruction exception.

* We adds initial configuration of PMA custom CSRs,
  and adds CSR reading and writing of PMA custom registers.

* NOTE: This patch adds some key config of PMA in Kconfig.

configs/riscv64-dual-xs-ref-debug_defconfig

@@ -62,6 +62,11 @@ CONFIG_RV_PMP_NUM=16
 CONFIG_RV_PMP_ACTIVE_NUM=16
 CONFIG_PMP_GRANULARITY=12
 CONFIG_RV_PMP_CHECK=y
+# CONFIG_RV_PMA_ENTRY_0 is not set
+CONFIG_RV_PMA_ENTRY_16=y
+CONFIG_RV_PMA_CSR=y
+CONFIG_RV_PMA_NUM=16
+CONFIG_RV_PMA_ACTIVE_NUM=16
 CONFIG_RV_SVINVAL=y
 # CONFIG_RV_SV39 is not set
 CONFIG_RV_SV48=y

configs/riscv64-dual-xs-ref_defconfig

@@ -63,6 +63,11 @@ CONFIG_RV_PMP_NUM=16
 CONFIG_RV_PMP_ACTIVE_NUM=16
 CONFIG_PMP_GRANULARITY=12
 CONFIG_RV_PMP_CHECK=y
+# CONFIG_RV_PMA_ENTRY_0 is not set
+CONFIG_RV_PMA_ENTRY_16=y
+CONFIG_RV_PMA_CSR=y
+CONFIG_RV_PMA_NUM=16
+CONFIG_RV_PMA_ACTIVE_NUM=16
 CONFIG_RV_SVINVAL=y
 # CONFIG_RV_SV39 is not set
 CONFIG_RV_SV48=y

configs/riscv64-xs-ref-debug_defconfig

@@ -62,6 +62,11 @@ CONFIG_RV_PMP_NUM=16
 CONFIG_RV_PMP_ACTIVE_NUM=16
 CONFIG_PMP_GRANULARITY=12
 CONFIG_RV_PMP_CHECK=y
+# CONFIG_RV_PMA_ENTRY_0 is not set
+CONFIG_RV_PMA_ENTRY_16=y
+CONFIG_RV_PMA_CSR=y
+CONFIG_RV_PMA_NUM=16
+CONFIG_RV_PMA_ACTIVE_NUM=16
 CONFIG_RV_SVINVAL=y
 # CONFIG_RV_SV39 is not set
 CONFIG_RV_SV48=y

configs/riscv64-xs-ref_defconfig

@@ -62,6 +62,11 @@ CONFIG_RV_PMP_NUM=16
 CONFIG_RV_PMP_ACTIVE_NUM=16
 CONFIG_PMP_GRANULARITY=12
 CONFIG_RV_PMP_CHECK=y
+# CONFIG_RV_PMA_ENTRY_0 is not set
+CONFIG_RV_PMA_ENTRY_16=y
+CONFIG_RV_PMA_CSR=y
+CONFIG_RV_PMA_NUM=16
+CONFIG_RV_PMA_ACTIVE_NUM=16
 CONFIG_RV_SVINVAL=y
 # CONFIG_RV_SV39 is not set
 CONFIG_RV_SV48=y

configs/riscv64-xs_defconfig

@@ -58,6 +58,11 @@ CONFIG_RV_PMP_CSR=y
 CONFIG_RV_PMP_NUM=16
 CONFIG_RV_PMP_ACTIVE_NUM=16
 CONFIG_PMP_GRANULARITY=12
+# CONFIG_RV_PMA_ENTRY_0 is not set
+CONFIG_RV_PMA_ENTRY_16=y
+CONFIG_RV_PMA_CSR=y
+CONFIG_RV_PMA_NUM=16
+CONFIG_RV_PMA_ACTIVE_NUM=16
 
 #
 # PMP Check Disabled when enabling PERF_OPT

src/isa/riscv64/Kconfig

@@ -360,6 +360,59 @@ config RV_PMP_CHECK
   bool "Enable PMP Check"
   default y
 
+choice
+  prompt "Number of implement PMA entries"
+  default RV_PMA_ENTRY_16
+  help
+    This config decided the number of PMA entries are implemented. An
+    attempt to access unimplemented PMA CSRs raises illegal-instruction
+    exception.
+
+    We supported up to 16 PMA entries.
+
+config RV_PMA_ENTRY_0
+  bool "0 PMA entry (Disabled)"
+  help
+    An attempt to access any pmacfg or pmaaddr CSRs raises an illegal-
+    instruction exception.
+
+config RV_PMA_ENTRY_16
+  bool "16 PMA entries"
+  help
+    Only pmacfg0, pmacfg2, pmaaddr0 - pmaaddr15 are accessible. An attempt
+    to access pmacfg4 - pmacfg14, pmaaddr16 - pmaaddr63 raises an illegal-
+    instruction exception.
+
+endchoice
+
+config RV_PMA_CSR
+  depends on RV_PMP_CSR
+  bool
+  default n if RV_PMA_ENTRY_0
+  default y
+
+config RV_PMA_NUM
+  int
+  default 0 if RV_PMA_ENTRY_0
+  default 16 if RV_PMA_ENTRY_16
+
+config RV_PMA_ACTIVE_NUM
+  depends on !RV_PMA_ENTRY_0
+  int "Number of active PMA entries"
+  range 0 16 if RV_PMA_ENTRY_16
+  default 16 if RV_PMA_ENTRY_16
+  help
+    This config decided the number of PMA entries are active. Implemented but
+    inactive PMA entries are read-only zero.
+
+    Any number of PMA entries may be read-only zero. NEMU assumes that the
+    lowest-numbered PMA entries are active, and the other are read-only zero.
+
+    For example, if
+      Number of implemented PMA entries = 16,
+    then
+      pmaaddr0 ~ pmaaddr15 are ready for use.
+
 config RV_SVINVAL
   bool "Enable VM Extension Svinval"
   default y

src/isa/riscv64/init.c

@@ -27,6 +27,7 @@ void init_trigger();
 void init_iprio();
 #endif
 void init_custom_csr();
+void init_pma();
 
 void init_riscv_timer();
 void init_device();
@@ -123,6 +124,10 @@ void init_isa() {
   pmpcfg14->val = 0;
 #endif // CONFIG_RV_PMP_ENTRY_64
 
+#ifdef CONFIG_RV_PMA_ENTRY_16
+  init_pma();
+#endif // CONFIG_RV_PMA_ENRTY_16
+
 #define ext(e) (1 << ((e) - 'a'))
   misa->extensions = ext('i') | ext('m') | ext('a') | ext('c') | ext('s') | ext('u');
 #ifndef CONFIG_FPU_NONE

src/isa/riscv64/local-include/csr.h

@@ -365,6 +365,19 @@
     f(pmpaddr60  , 0x3EC) f(pmpaddr61  , 0x3ED) f(pmpaddr62  , 0x3EE) f(pmpaddr63  , 0x3EF)
 #endif // CONFIG_RV_PMP_ENTRY_64
 
+/** Machine Memory Attributes (PMA) **/
+#ifdef CONFIG_RV_PMA_ENTRY_0
+  #define CSRS_M_MEMORY_ATTRIBUTE(f)
+#endif // CONFIG_RV_PMA_ENTRY_0
+#ifdef CONFIG_RV_PMA_ENTRY_16
+  #define CSRS_M_MEMORY_ATTRIBUTE(f) \
+    f(pmacfg0   , 0x7C0) f(pmacfg2    , 0x7C2) \
+    f(pmaaddr0  , 0x7C8) f(pmaaddr1   , 0x7C9) f(pmaaddr2   , 0x7CA) f(pmaaddr3   , 0x7CB) \
+    f(pmaaddr4  , 0x7CC) f(pmaaddr5   , 0x7CD) f(pmaaddr6   , 0x7CE) f(pmaaddr7   , 0x7CF) \
+    f(pmaaddr8  , 0x7D0) f(pmaaddr9   , 0x7D1) f(pmaaddr10  , 0x7D2) f(pmaaddr11  , 0x7D3) \
+    f(pmaaddr12 , 0x7D4) f(pmaaddr13  , 0x7D5) f(pmaaddr14  , 0x7D6) f(pmaaddr15  , 0x7D7)
+#endif // CONFIG_RV_PMA_ENTRY_16
+
 /** Machine State Enable Registers **/
 #ifdef CONFIG_RV_SMSTATEEN
   #define CSRS_M_STATE_ENABLE(f) \
@@ -475,6 +488,7 @@
   CSRS_M_TRAP_HANDLING(f) \
   CSRS_M_CONFIGURATION(f) \
   CSRS_M_MEMORY_PROTECTION(f) \
+  CSRS_M_MEMORY_ATTRIBUTE(f) \
   CSRS_M_STATE_ENABLE(f) \
   CSRS_M_NON_MASKABLE_INTERRUPT_HANDLING(f) \
   CSRS_M_COUNTER_TIMERS(f) \
@@ -789,6 +803,10 @@ CSR_STRUCT_END(mtinst)
 
 CSR_STRUCT_DUMMY_LIST(CSRS_M_MEMORY_PROTECTION)
 
+/** Physical Memory Attributes CSRs */
+
+CSR_STRUCT_DUMMY_LIST(CSRS_M_MEMORY_ATTRIBUTE)
+
 /** Debug Mode Registers (Core Debug Registers) **/
 
 #ifdef CONFIG_RV_SDEXT
@@ -1525,6 +1543,25 @@ MAP(CSRS, CSRS_DECL)
 #define CSR_PMPCFG_MAX_NUM  16
 #define CSR_PMPADDR_MAX_NUM 64
 
+/** Machine Memory Attributes (PMA) **/
+#define PMA_R     PMP_R
+#define PMA_W     PMP_W
+#define PMA_X     PMP_X
+#define PMA_A     PMP_A
+#define PMA_T     0x20
+#define PMA_C     0x40
+#define PMA_L     PMP_L
+#define PMA_SHIFT PMP_SHIFT
+
+#define PMA_TOR   PMP_TOR
+#define PMA_NA4   PMP_NA4
+#define PMA_NAPOT PMP_NAPOT
+
+#define CSR_PMACFG_BASE     0x7c0
+#define CSR_PMAADDR_BASE    0x7c8
+#define CSR_PMACFG_MAX_NUM  2
+#define CSR_PMAADDR_MAX_NUM 16
+
 /** Vector **/
 #define IDXVSTART 0x008
 #define IDXVXSAT  0x009
@@ -1633,4 +1670,8 @@ uint8_t pmpcfg_from_index(int idx);
 word_t pmpaddr_from_index(int idx);
 word_t pmp_tor_mask();
 
+/** PMA */
+uint8_t pmacfg_from_index(int idx);
+word_t pmaaddr_from_index(int idx);
+
 #endif // __CSR_H__

src/isa/riscv64/local-include/reg.h

@@ -41,4 +41,20 @@ static inline const char* fpreg_name(int index, int width){
   return fpregsl[index];
 }
 
+typedef struct {
+  uint64_t base_addr;
+  uint64_t range;
+  uint64_t l;
+  uint64_t c;
+  uint64_t t; // atomic
+  uint64_t a;
+  uint64_t x;
+  uint64_t w;
+  uint64_t r;
+} PMAConfig;
+
+typedef struct PMAConfigModule {
+  PMAConfig pmaconfigs[CONFIG_RV_PMA_ACTIVE_NUM];
+} PMAConfigModule;
+
 #endif

src/isa/riscv64/reg.c

@@ -228,6 +228,16 @@ void isa_reg_display() {
     #endif
   #endif // CONFIG_RV_PMP_CSR
 
+  #ifdef CONFIG_RV_PMA_CSR
+    DISPLAY_HR("PMA CSRs");
+    printf("pma: %d entries active, details:\n", CONFIG_RV_PMA_ACTIVE_NUM);
+    for (int i = 0; i < CONFIG_RV_PMA_NUM; i++) {
+      printf("%2d: cfg:0x%02x addr:0x%016lx", i, pmacfg_from_index(i), pmaaddr_from_index(i));
+      if (i % 2 == 1) printf("\n");
+      else printf("|");
+    }
+  #endif // CONFIG_RV_PMA_CSR
+
   #ifdef CONFIG_RVV
     //vector register
     DISPLAY_HR("Vector Registers");