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difftest: fix vec too long bug
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xiaokamikami committed May 20, 2024
1 parent 8ac81ec commit 62b6df9
Showing 1 changed file with 7 additions and 5 deletions.
12 changes: 7 additions & 5 deletions src/main/scala/Gateway.scala
Original file line number Diff line number Diff line change
Expand Up @@ -99,6 +99,7 @@ case class GatewayResult(
object Gateway {
private val instances = ListBuffer.empty[DifftestBundle]
private var config = GatewayConfig()

def setConfig(cfg: String): Unit = {
cfg.foreach {
case 'E' => config = config.copy(hasGlobalEnable = true)
Expand Down Expand Up @@ -265,14 +266,15 @@ class Preprocess(bundles: Seq[DifftestBundle], config: GatewayConfig, numcores:
if (config.hasDutZone || config.isSquash || config.isBatch) {
// Special fix for int writeback. Work for single-core only
if (in.exists(_.desiredCppName == "wb_int")) {
//require(in.count(_.isUniqueIdentifier) == 1, "only single-core is supported yet")
if (config.isSquash || config.isBatch) {
require(in.count(_.isUniqueIdentifier) == 1, "only single-core is supported yet")
}
val writebacks = in.filter(_.desiredCppName == "wb_int").map(_.asInstanceOf[DiffIntWriteback])
val coreid = writebacks.head.coreid
val numPhyRegs = writebacks.head.numElements
val wb_int = Reg(Vec(numcores, Vec(numPhyRegs, UInt(64.W))))
val wb_int = Reg(Vec(numcores,Vec(numPhyRegs,UInt(64.W))))
for (wb <- writebacks) {
when(wb.valid) {
wb_int(coreid)(wb.address) := wb.data
wb_int(wb.coreid)(wb.address) := wb.data
}
}

Expand All @@ -284,7 +286,7 @@ class Preprocess(bundles: Seq[DifftestBundle], config: GatewayConfig, numcores:
when(c.valid && c.skip) {
wb_for_skip.valid := true.B
wb_for_skip.address := c.wpdest
wb_for_skip.data := wb_int(coreid)(c.wpdest)
wb_for_skip.data := wb_int(c.coreid)(c.wpdest)
for (wb <- writebacks) {
when(wb.valid && wb.address === c.wpdest) {
wb_for_skip.data := wb.data
Expand Down

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