boards: cubepilot_cubeorange lower cpu clock 480 -> 400 MHz to reduce…

… temperature
PX4 · Oct 25, 2021 · 8e2cb07 · 8e2cb07
1 parent f4c21ce
commit 8e2cb07
Showing 1 changed file with 32 additions and 32 deletions.
diff --git a/boards/cubepilot/cubeorange/nuttx-config/include/board.h b/boards/cubepilot/cubeorange/nuttx-config/include/board.h
@@ -86,52 +86,52 @@
 
 /* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
  *
- *   PLL1_VCO = (24,000,000 / 2) * 80 = 960 MHz
+ *   PLL1_VCO = (24,000,000 / 3) * 100 = 800 MHz
  *
- *   PLL1P = PLL1_VCO/2  = 960 MHz / 2   = 480 MHz
- *   PLL1Q = PLL1_VCO/4  = 960 MHz / 4   = 240 MHz
- *   PLL1R = PLL1_VCO/8  = 960 MHz / 8   = 120 MHz
+ *   PLL1P = PLL1_VCO/2  = 800 MHz / 2   = 400 MHz
+ *   PLL1Q = PLL1_VCO/8  = 800 MHz / 8   = 100 MHz
+ *   PLL1R = PLL1_VCO/2  = 800 MHz / 2   = 400 MHz
  */
 #define STM32_PLLCFG_PLL1CFG    (RCC_PLLCFGR_PLL1VCOSEL_WIDE|RCC_PLLCFGR_PLL1RGE_4_8_MHZ|RCC_PLLCFGR_DIVP1EN|RCC_PLLCFGR_DIVQ1EN|RCC_PLLCFGR_DIVR1EN)
-#define STM32_PLLCFG_PLL1M       RCC_PLLCKSELR_DIVM1(2)
-#define STM32_PLLCFG_PLL1N       RCC_PLL1DIVR_N1(80)
+#define STM32_PLLCFG_PLL1M       RCC_PLLCKSELR_DIVM1(3)
+#define STM32_PLLCFG_PLL1N       RCC_PLL1DIVR_N1(100)
 #define STM32_PLLCFG_PLL1P       RCC_PLL1DIVR_P1(2)
-#define STM32_PLLCFG_PLL1Q       RCC_PLL1DIVR_Q1(4)
-#define STM32_PLLCFG_PLL1R       RCC_PLL1DIVR_R1(8)
+#define STM32_PLLCFG_PLL1Q       RCC_PLL1DIVR_Q1(8)
+#define STM32_PLLCFG_PLL1R       RCC_PLL1DIVR_R1(2)
 
-#define STM32_VCO1_FREQUENCY     ((STM32_HSE_FREQUENCY / 2) * 80)
+#define STM32_VCO1_FREQUENCY     ((STM32_HSE_FREQUENCY / 3) * 100)
 #define STM32_PLL1P_FREQUENCY    (STM32_VCO1_FREQUENCY / 2)
-#define STM32_PLL1Q_FREQUENCY    (STM32_VCO1_FREQUENCY / 4)
-#define STM32_PLL1R_FREQUENCY    (STM32_VCO1_FREQUENCY / 8)
+#define STM32_PLL1Q_FREQUENCY    (STM32_VCO1_FREQUENCY / 8)
+#define STM32_PLL1R_FREQUENCY    (STM32_VCO1_FREQUENCY / 2)
 
 /* PLL2 */
 #define STM32_PLLCFG_PLL2CFG     (RCC_PLLCFGR_PLL2VCOSEL_WIDE|RCC_PLLCFGR_PLL2RGE_4_8_MHZ|RCC_PLLCFGR_DIVP2EN|RCC_PLLCFGR_DIVQ2EN|RCC_PLLCFGR_DIVR2EN)
-#define STM32_PLLCFG_PLL2M       RCC_PLLCKSELR_DIVM2(4)
-#define STM32_PLLCFG_PLL2N       RCC_PLL2DIVR_N2(32)
+#define STM32_PLLCFG_PLL2M       RCC_PLLCKSELR_DIVM2(2)
+#define STM32_PLLCFG_PLL2N       RCC_PLL2DIVR_N2(30)
 #define STM32_PLLCFG_PLL2P       RCC_PLL2DIVR_P2(2)
-#define STM32_PLLCFG_PLL2Q       RCC_PLL2DIVR_Q2(2)
-#define STM32_PLLCFG_PLL2R       RCC_PLL2DIVR_R2(2)
+#define STM32_PLLCFG_PLL2Q       RCC_PLL2DIVR_Q2(5)
+#define STM32_PLLCFG_PLL2R       RCC_PLL2DIVR_R2(1)
 
-#define STM32_VCO2_FREQUENCY     ((STM32_HSE_FREQUENCY / 4) * 32)
+#define STM32_VCO2_FREQUENCY     ((STM32_HSE_FREQUENCY / 2) * 30)
 #define STM32_PLL2P_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
-#define STM32_PLL2Q_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
-#define STM32_PLL2R_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
+#define STM32_PLL2Q_FREQUENCY    (STM32_VCO2_FREQUENCY / 5)
+#define STM32_PLL2R_FREQUENCY    (STM32_VCO2_FREQUENCY / 1)
 
 /* PLL3 */
 #define STM32_PLLCFG_PLL3CFG    (RCC_PLLCFGR_PLL3VCOSEL_WIDE|RCC_PLLCFGR_PLL3RGE_4_8_MHZ|RCC_PLLCFGR_DIVQ3EN)
-#define STM32_PLLCFG_PLL3M      RCC_PLLCKSELR_DIVM3(4)
-#define STM32_PLLCFG_PLL3N      RCC_PLL3DIVR_N3(32)
-#define STM32_PLLCFG_PLL3P      RCC_PLL3DIVR_P3(2)
-#define STM32_PLLCFG_PLL3Q      RCC_PLL3DIVR_Q3(4)
-#define STM32_PLLCFG_PLL3R      RCC_PLL3DIVR_R3(2)
-
-#define STM32_VCO3_FREQUENCY    ((STM32_HSE_FREQUENCY / 4) * 32)
-#define STM32_PLL3P_FREQUENCY   (STM32_VCO3_FREQUENCY / 2)
-#define STM32_PLL3Q_FREQUENCY   (STM32_VCO3_FREQUENCY / 4)
-#define STM32_PLL3R_FREQUENCY   (STM32_VCO3_FREQUENCY / 2)
-
-/* SYSCLK = PLL1P = 480MHz
- * CPUCLK = SYSCLK / 1 = 480 MHz
+#define STM32_PLLCFG_PLL3M      RCC_PLLCKSELR_DIVM3(6)
+#define STM32_PLLCFG_PLL3N      RCC_PLL3DIVR_N3(72)
+#define STM32_PLLCFG_PLL3P      RCC_PLL3DIVR_P3(3)
+#define STM32_PLLCFG_PLL3Q      RCC_PLL3DIVR_Q3(6)
+#define STM32_PLLCFG_PLL3R      RCC_PLL3DIVR_R3(9)
+
+#define STM32_VCO3_FREQUENCY    ((STM32_HSE_FREQUENCY / 6) * 72)
+#define STM32_PLL3P_FREQUENCY   (STM32_VCO3_FREQUENCY / 3)
+#define STM32_PLL3Q_FREQUENCY   (STM32_VCO3_FREQUENCY / 6)
+#define STM32_PLL3R_FREQUENCY   (STM32_VCO3_FREQUENCY / 9)
+
+/* SYSCLK = PLL1P = 400MHz
+ * CPUCLK = SYSCLK / 1 = 400 MHz
  */
 #define STM32_RCC_D1CFGR_D1CPRE  (RCC_D1CFGR_D1CPRE_SYSCLK)
 #define STM32_SYSCLK_FREQUENCY   (STM32_PLL1P_FREQUENCY)
@@ -140,7 +140,7 @@
 /* Configure Clock Assignments */
 
 /* AHB clock (HCLK) is SYSCLK/2 (240 MHz max)
- * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 240
+ * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 200
  */
 #define STM32_RCC_D1CFGR_HPRE   RCC_D1CFGR_HPRE_SYSCLKd2        /* HCLK  = SYSCLK / 2 */
 #define STM32_ACLK_FREQUENCY    (STM32_CPUCLK_FREQUENCY / 2)    /* ACLK in D1, HCLK3 in D1 */