[SC64][FW][SW] Moved CIC emulation from MCU to FPGA (#56)

Polprzewodnikowy · Dec 14, 2023 · ff27e35 · ff27e35
1 parent e019808
commit ff27e35
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diff --git a/.gitattributes b/.gitattributes
@@ -1,4 +1,5 @@
 fw/project/lcmxo2/*.sty linguist-generated
+fw/rtl/serv/* -linguist-vendored
 fw/rtl/vendor/** -linguist-vendored
 fw/rtl/vendor/lcmxo2/generated/* linguist-generated
 hw/pcb/*.html linguist-generated

diff --git a/README.md b/README.md
@@ -13,6 +13,7 @@
  - 64DD add-on emulation
  - IS-Viewer 64 debug interface
  - N64 bootloader with support for IPL3 registers spoofing and loading menu from SD card
+ - Dedicated open source menu written specifically for this flashcart - [N64FlashcartMenu](https://github.com/Polprzewodnikowy/N64FlashcartMenu)
  - Enhanced [UltraCIC_C](https://github.com/jago85/UltraCIC_C) emulation with automatic region switching and programmable seed/checksum values
  - PC app for communicating with flashcart (game/save data upload/download, feature enable control and debug terminal)
  - [UNFLoader](https://github.com/buu342/N64-UNFLoader) support
@@ -47,8 +48,15 @@ I'm also active at [N64brew](https://discord.gg/WqFgNWf) Discord server as `korg
 
 One option is to ask in `#summer-cart-64` channel on [N64brew](https://discord.gg/WqFgNWf) Discord server if someone is making a group order.
 
-If you want to order it yourself then I've prepared all necessary manufacturing files on [PCBWay Shared Project](https://www.pcbway.com/project/shareproject/SC64_an_open_source_Nintendo_64_flashcart_14b9688a.html) site.
-Full disclosure: for every order made through this link I will receive 10% of PCB manufacturing and PCB assembly service cost. This is a great way of supporting further project development.
+If you want to order it yourself then I've prepared all necessary manufacturing files on the [PCBWay Shared Project](https://www.pcbway.com/project/shareproject/SC64_an_open_source_Nintendo_64_flashcart_14b9688a.html) site.
+
+**Full disclosure**: for every order made through [this link](https://www.pcbway.com/project/shareproject/SC64_an_open_source_Nintendo_64_flashcart_14b9688a.html) I will receive 10% of PCB manufacturing and PCB assembly service cost (price of the components is not included in the split). This is a great way of supporting further project development.
+
+**Be careful**: this is an advanced project and it is assumed that you have enough knowledge about electronics.
+Selecting wrong options or giving PCB manufacturer wrong information might result in an undesired time and/or money loss.
+Boards also come unprogrammed from the manufacturer - you need to do **initial programming step** yourself after receiving the board.
+To avoid problems _**please**_ read **both** [build guide](./docs/06_build_guide.md) and description on the shared project page **in full**.
+If you have even slightest doubt about the ordering or programming process, it is better to leave it to someone experienced - ask in the Discord server mentioned above if that's the case.
 
 If you don't need a physical product but still want to support me then check my [GitHub sponsors](https://github.com/sponsors/Polprzewodnikowy) page.
 
@@ -63,7 +71,9 @@ If you don't need a physical product but still want to support me then check my
 ## Finished example
 
 [<img src="assets/sc64_finished_example.jpg" alt="SC64 finished example" width="800" />](assets/sc64_finished_example.jpg)
+
 [<img src="assets/sc64_pcb_front.jpg" alt="SC64 PCB front" width="800" />](assets/sc64_pcb_front.jpg)
+
 [<img src="assets/sc64_pcb_back.jpg" alt="SC64 PCB back" width="800" />](assets/sc64_pcb_back.jpg)
 
 ---
@@ -81,3 +91,4 @@ This project wouldn't be possible without these contributions:
 - [FatFs](http://elm-chan.org/fsw/ff/00index_e.html) FAT32/exFAT library being easiest to integrate in embedded environment.
 - [Yakumono's (@LuigiBlood)](https://twitter.com/LuigiBlood) extensive [64DD documentation](https://github.com/LuigiBlood/64dd/wiki) and its implementation in various emulators.
 - [Libdragon](https://github.com/DragonMinded/libdragon) open source N64 SDK project and its developers.
+- [SERV](https://github.com/olofk/serv) bit-serial 32-bit RISC-V CPU soft core.
diff --git a/assets/sc64_block_diagram.svg b/assets/sc64_block_diagram.svg
diff --git a/build.sh b/build.sh
@@ -29,6 +29,7 @@ FILES=(
 
 BUILT_BOOTLOADER=false
 BUILT_CONTROLLER=false
+BUILT_CIC=false
 BUILT_FPGA=false
 BUILT_UPDATE=false
 BUILT_RELEASE=false
@@ -66,6 +67,19 @@ build_controller () {
     BUILT_CONTROLLER=true
 }
 
+build_cic () {
+    if [ "$BUILT_CIC" = true ]; then return; fi
+
+    pushd sw/cic > /dev/null
+    if [ "$FORCE_CLEAN" = true ]; then
+        ./build.sh clean
+    fi
+    ./build.sh all
+    popd > /dev/null
+
+    BUILT_CIC=true
+}
+
 build_fpga () {
     if [ "$BUILT_FPGA" = true ]; then return; fi
 
@@ -84,6 +98,7 @@ build_update () {
 
     build_bootloader
     build_controller
+    build_cic
     build_fpga
 
     pushd sw/tools > /dev/null
@@ -126,10 +141,11 @@ build_release () {
 
 print_usage () {
     echo "builder script for SC64"
-    echo "usage: ./build.sh [bootloader] [controller] [fpga] [update] [release] [-c] [--help]"
+    echo "usage: ./build.sh [bootloader] [controller] [cic] [fpga] [update] [release] [-c] [--help]"
     echo "parameters:"
     echo "  bootloader  - compile N64 bootloader software"
     echo "  controller  - compile MCU controller software"
+    echo "  cic         - compile CIC emulation software"
     echo "  fpga        - compile FPGA design"
     echo "  update      - compile all software and designs"
     echo "  release     - collect and zip files for release (triggers 'update' build)"
@@ -147,6 +163,7 @@ fi
 
 TRIGGER_BOOTLOADER=false
 TRIGGER_CONTROLLER=false
+TRIGGER_CIC=false
 TRIGGER_FPGA=false
 TRIGGER_UPDATE=false
 TRIGGER_RELEASE=false
@@ -159,6 +176,9 @@ while test $# -gt 0; do
         controller)
             TRIGGER_CONTROLLER=true
             ;;
+        cic)
+            TRIGGER_CIC=true
+            ;;
         fpga)
             TRIGGER_FPGA=true
             ;;
@@ -187,6 +207,7 @@ done
 
 if [ "$TRIGGER_BOOTLOADER" = true ]; then build_bootloader; fi
 if [ "$TRIGGER_CONTROLLER" = true ]; then build_controller; fi
+if [ "$TRIGGER_CIC" = true ]; then build_cic; fi
 if [ "$TRIGGER_FPGA" = true ]; then build_fpga; fi
 if [ "$TRIGGER_UPDATE" = true ]; then build_update; fi
 if [ "$TRIGGER_RELEASE" = true ]; then build_release; fi
diff --git a/docker_build.sh b/docker_build.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 
-BUILDER_IMAGE="ghcr.io/polprzewodnikowy/sc64env:v1.5"
+BUILDER_IMAGE="ghcr.io/polprzewodnikowy/sc64env:v1.8"
 
 pushd $(dirname $0) > /dev/null
 

diff --git a/docs/02_n64_commands.md b/docs/02_n64_commands.md
@@ -7,11 +7,11 @@
 | id  | name                  | arg0           | arg1         | rsp0             | rsp1           | description                                                |
 | --- | --------------------- | -------------- | ------------ | ---------------- | -------------- | ---------------------------------------------------------- |
 | `v` | **IDENTIFIER_GET**    | ---            | ---          | identifier       | ---            | Get flashcart identifier `SCv2`                            |
-| `V` | **VERSION_GET**       | ---            | ---          | version          | ---            | Get flashcart firmware version                             |
+| `V` | **VERSION_GET**       | ---            | ---          | major/minor      | revision       | Get flashcart firmware version                             |
 | `c` | **CONFIG_GET**        | config_id      | ---          | ---              | current_value  | Get config option                                          |
 | `C` | **CONFIG_SET**        | config_id      | new_value    | ---              | previous_value | Set config option and get previous value                   |
-| `c` | **SETTING_GET**       | setting_id     | ---          | ---              | current_value  | Get persistent setting option                              |
-| `C` | **SETTING_SET**       | setting_id     | new_value    | ---              | ---            | Set persistent setting option                              |
+| `a` | **SETTING_GET**       | setting_id     | ---          | ---              | current_value  | Get persistent setting option                              |
+| `A` | **SETTING_SET**       | setting_id     | new_value    | ---              | ---            | Set persistent setting option                              |
 | `t` | **TIME_GET**          | ---            | ---          | time_0           | time_1         | Get current RTC value                                      |
 | `T` | **TIME_SET**          | time_0         | time_1       | ---              | ---            | Set new RTC value                                          |
 | `m` | **USB_READ**          | pi_address     | length       | ---              | ---            | Receive data from USB to flashcart                         |
@@ -23,7 +23,7 @@
 | `s` | **SD_READ**           | pi_address     | sector_count | ---              | ---            | Read sectors from SD card to flashcart                     |
 | `S` | **SD_WRITE**          | pi_address     | sector_count | ---              | ---            | Write sectors from flashcart to SD card                    |
 | `D` | **DISK_MAPPING_SET**  | pi_address     | table_size   | ---              | ---            | Set 64DD disk mapping for SD mode                          |
-| `w` | **WRITEBACK_PENDING** | pending_status | ---          | ---              | ---            | Get save writeback status (is write queued to the SD card) |
+| `w` | **WRITEBACK_PENDING** | ---            | ---          | pending_status   | ---            | Get save writeback status (is write queued to the SD card) |
 | `W` | **WRITEBACK_SD_INFO** | pi_address     | ---          | ---              | ---            | Load writeback SD sector table and enable it               |
 | `K` | **FLASH_PROGRAM**     | pi_address     | length       | ---              | ---            | Program flash with bytes loaded into data buffer           |
 | `p` | **FLASH_WAIT_BUSY**   | wait           | ---          | erase_block_size | ---            | Wait until flash ready / get block erase size              |

diff --git a/fw/project/lcmxo2/debug.sty b/fw/project/lcmxo2/debug.sty
diff --git a/fw/project/lcmxo2/release.sty b/fw/project/lcmxo2/release.sty
diff --git a/fw/project/lcmxo2/sc64.ldf b/fw/project/lcmxo2/sc64.ldf
@@ -6,6 +6,12 @@
         <Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
+        <Source name="../../rtl/n64/n64_scb.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../rtl/sd/sd_scb.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
         <Source name="../../rtl/fifo/fifo_bus.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
@@ -33,9 +39,15 @@
         <Source name="../../rtl/memory/memory_sdram.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
+        <Source name="../../rtl/n64/n64_reg_bus.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
         <Source name="../../rtl/n64/n64_cfg.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
+        <Source name="../../rtl/n64/n64_cic.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
         <Source name="../../rtl/n64/n64_dd.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
@@ -48,15 +60,9 @@
         <Source name="../../rtl/n64/n64_pi_fifo.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
-        <Source name="../../rtl/n64/n64_reg_bus.sv" type="Verilog" type_short="Verilog">
-            <Options VerilogStandard="System Verilog"/>
-        </Source>
         <Source name="../../rtl/n64/n64_save_counter.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
-        <Source name="../../rtl/n64/n64_scb.sv" type="Verilog" type_short="Verilog">
-            <Options VerilogStandard="System Verilog"/>
-        </Source>
         <Source name="../../rtl/n64/n64_si.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
@@ -78,9 +84,6 @@
         <Source name="../../rtl/sd/sd_dat.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
-        <Source name="../../rtl/sd/sd_scb.sv" type="Verilog" type_short="Verilog">
-            <Options VerilogStandard="System Verilog"/>
-        </Source>
         <Source name="../../rtl/sd/sd_top.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
@@ -108,6 +111,54 @@
         <Source name="../../rtl/vendor/lcmxo2/generated/pll_lattice_generated.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
+        <Source name="../../rtl/serv/serv_aligner.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_alu.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_bufreg.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_bufreg2.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_compdec.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_csr.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_ctrl.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_decode.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_immdec.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_mem_if.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_rf_if.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_rf_ram.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_rf_ram_if.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_rf_top.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_state.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../rtl/serv/serv_top.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
         <Source name="../../rtl/top.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog" top_module="top"/>
         </Source>