NAND Gate

• Abstract
• Reference circuit
• Reference waveform
• Synopsis simulation
  • Schematic
  • Input A parameters
  • Input B parameters
  • Testbench settings
  • Netlist
  • Waveform
• conclusion
• Acknowledgement
• References

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Abstract

NAND gate is a universal logic gate. It is an important gate because any logical circuit can be created using NAND gate only. Here I have implemented 2 input NAND gate. It has two inputs (Input A and input B) and a single output. The logical equation for NAND gate is Y= (A.B)'

Reference circuit

NAND gate is a universal logic gate. Here, 2 PMOS and 2 NMOS transistors have been used to create a 2 input NAND gate using CMOS technology. Both PMOS transistors are connected in parallel. They insure that output is pulled to high logic level when any one of the input is low. The NMOS transistors are connected in series and they pull the output to low logic level only when both inputs are high. Thus, at the output we get (A.B)'

Reference Waveform

Simulation in Synopsys

Schematic:

Input A parameters:

Input B parameters:

Testbench settings:

Netlist:

*  Generated for: PrimeSim
*  Design library name: NAND_gate
*  Design cell name: NAND_gate_2_tb
*  Design view name: schematic
.lib 'saed32nm.lib' TT

*Custom Compiler Version S-2021.09
*Fri Feb 25 12:05:59 2022

.global gnd!
********************************************************************************
* Library          : NAND_gate
* Cell             : NAND_gate_2
* View             : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List   : hspice hspiceD
********************************************************************************
.subckt nand_gate_2 gnd_1 in1 in2 out vdd
xm4 out in2 vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm0 out in1 vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm3 net11 in2 gnd_1 gnd_1 n105 w=0.1u l=0.03u nf=1 m=1
xm2 out in1 net11 net11 n105 w=0.1u l=0.03u nf=1 m=1
.ends nand_gate_2

********************************************************************************
* Library          : NAND_gate
* Cell             : NAND_gate_2_tb
* View             : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List   : hspice hspiceD
********************************************************************************
xi0 gnd! net8 net10 net16 net7 nand_gate_2
v1 net7 gnd! dc=1.8
v3 net10 gnd! dc=0 pulse ( 0 1.05 0 0.1u 0.1u 10u 20u )
v2 net8 gnd! dc=0 pulse ( 0 1.05 0 0.1u 0.1u 5u 10u )
c9 net16 gnd! c=1p

.tran '1u' '40u' name=tran

.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1
.probe tran v(net10) v(net16) v(net8)

.temp 25

.option primesim_output=wdf

.option parhier = LOCAL

.end

Waveform:

Conclusion

Thus the working of NAND gate using 28nm CMOS technology is verified.

Acknowledgement

1. Synopsys Team/Company
2. Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalpghosh@gmail.com
3. Chinmaya Panda, IIT Hyderabad

References

1. Kapil Mangla, Prof. (Dr.) Anil Kumar “Study and analysis of NOT & NAND gate using various low power Techniques” International Journal of Scientific & Engineering Research, Volume 7, Issue 1
2. Ginni Jain, Keerti Vyas “Comparative analysis of universal gates using MCML and CMOS technique” International Journal of Computer Applications (0975 – 8887) Volume 118 – No. 5