Pyverilog 0.6.0 for public.

Makefile

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+.PHONY: all
+all:
+	make -C ./vparser
+	make -C ./definition_analyzer
+	make -C ./definition_resolver
+	make -C ./optimizer
+	make -C ./tree_constructor
+	make -C ./tree_walker
+	make -C ./graph
+	make -C ./subset
+	make -C ./codegen	
+	make -C ./controlflow
+	make -C ./active_condition
+	make -C ./ast_to_code
+
+.PHONY: clean
+clean:
+	make clean -C ./utils
+	make clean -C ./vparser
+	make clean -C ./definition_analyzer
+	make clean -C ./definition_resolver
+	make clean -C ./optimizer
+	make clean -C ./tree_constructor
+	make clean -C ./tree_walker
+	make clean -C ./graph
+	make clean -C ./subset
+	make clean -C ./codegen	
+	make clean -C ./controlflow
+	make clean -C ./active_condition
+	make clean -C ./ast_to_code
+	rm -rf *.pyc __pycache__ *.out parsetab.py *.html

README.md

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+Pyverilog
+==============================
+Python-based Tool-chain for design analysis and code generation of Verilog HDL
+
+Copyright (C) 2013, Shinya Takamaeda-Yamazaki
+
+E-mail: takamaeda\_at\_arch.cs.titech.ac.jp
+
+License
+------------------------------
+Apache License 2.0
+(http://www.apache.org/licenses/LICENSE-2.0)
+
+
+This software package includes PLY-3.4 in "vparser/ply".
+The license of PLY is BSD.
+
+
+What's Pyverilog?
+------------------------------
+
+Pyverilog is open-source design analyzer/generator of Verilog HDL. All source codes are written in Python.
+
+Pyverilog includes various independent software tools for Verilog HDL.
+You can create your own design analyzer, code translator and code generator for Verilog HDL based on this tool-chain.
+
+
+Software Requirements
+------------------------------
+
+* Python (2.7 and 3.3 or later)
+   - 'controlflow' and 'graph' use Python 2.7 to generate a graph image using python-graphviz
+* Jinja2 (2.7 or later)
+   - pip3 install jinja2
+* Icarus Verilog (0.9.6 or later)
+   - apt-get install iverilog
+
+
+Getting Started
+------------------------------
+
+This software includes various tools for Verilog HDL design.
+
+Most useful tools are
+
+* vparser: Code parser to generate AST (Abstract Syntax Tree) from source codes of Verilog HDL.
+* definition\_analyzer: Dataflow analyzer.
+* optimizer: Definition optimizer to remove redundant expressions.
+* ast\_to\_code: Code generator of Verilog HDL from AST
+
+The other tools are useful for control-flow analysis and active value inference to generate some accelerated logics.
+
+To use them, plase type just 'make' in each sub directory.
+

__init__.py

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+import sys
+if sys.version_info[0] < 3:
+    import utils
+    import vparser
+    import definition_analyzer
+    import definition_resolver
+    import optimizer
+    import tree_constructor
+    import tree_walker
+    import graph
+    import subset
+    import codegen	
+    import controlflow
+    import active_condition
+    #import ast_to_code # Python 2.x does not support

active_condition/Makefile

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+PYTHON=python3.3
+#OPT=-m pdb
+
+ACTIVE=active_condition.py
+SRCS=../test/vectoradd.v
+TOP=-t TOP
+TARGETS=-s "TOP.MEM_RE"
+
+.PHONY: active
+active:
+	$(PYTHON) $(OPT) $(ACTIVE) $(TOP) $(SRCS) $(TARGETS) 
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

active_condition/__init__.py

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+import sys
+if sys.version_info[0] < 3:
+    import active_condition
+    import active_range

active_condition/active_condition.py

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+#-------------------------------------------------------------------------------
+# active_condition.py
+#
+# Active condition list generator from Verilog Definitions with Pyverilog
+#
+# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
+# License: Apache 2.0
+#-------------------------------------------------------------------------------
+
+import sys
+import os
+
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+
+import pyverilog.utils.version
+import pyverilog.utils.util as util
+import pyverilog.utils.tree_reorder as tree_reorder
+import pyverilog.utils.tree_splitter as tree_splitter
+import pyverilog.utils.inference as inference
+import pyverilog.utils.state_transition as state_transition
+from pyverilog.utils.dataflow import *
+
+from pyverilog.controlflow.controlflow import VerilogControlflow
+
+class VerilogActiveCondition(VerilogControlflow):
+    def __init__(self, topmodule, terms, binddict, 
+                 resolved_terms, resolved_binddict, constlist):
+        VerilogControlflow.__init__(self, topmodule, terms, binddict, 
+                                    resolved_terms, resolved_binddict, constlist)
+        self.fsm_loops, self.fsms = self.getLoops()
+
+    ############################################################################
+    def getActiveConditions(self, termname, condition=tree_splitter.active_constant):
+        if not termname in self.resolved_binddict: return {}
+        tree = self.makeTree(termname)
+        funcdict = tree_splitter.split(tree)
+        funcdict = tree_splitter.filter(funcdict, termname, condition)
+        funcdict = tree_splitter.remove_reset_condition(funcdict)
+
+        if len(funcdict) == 1 and len(list(funcdict.keys())[0]) == 0:
+            func = funcdict.values()[0]
+            return {termname : ( ('any', None), )}
+
+        active_conditions = {}
+        active_conditions_size = 0
+        for fsm_sig in self.fsms.keys():
+            rslt = self.getActiveConditions_fsm(fsm_sig, funcdict)
+            if len(rslt) > 0: active_conditions[fsm_sig] = rslt
+            active_conditions_size += len(rslt)
+
+        if active_conditions_size == 0:
+            rslt = self.getActiveConditions_fsm(termname, funcdict)
+            if len(rslt) > 0: active_conditions[termname] = rslt
+
+        return active_conditions
+
+    def getActiveConditions_fsm(self, fsm_sig, funcdict):
+        # returns a list of some (state, transcond) pairs
+        active_conditions = []
+        fsm_sig_width = self.getWidth(fsm_sig)
+        for condlist, func in sorted(funcdict.items(), key=lambda x:len(x[0])):
+            node = state_transition.walkCondlist(condlist, fsm_sig, fsm_sig_width)
+            state_node_list = []
+            if isinstance(node, state_transition.StateNodeList):
+                for n in node.nodelist: state_node_list.append(n)
+            elif node:
+                state_node_list.append(node)
+
+            for state_node in state_node_list:
+                #if state_node.isany:
+                #    active_conditions.append( ('any', state_node.transcond) )
+                for rs, re in state_node.range_pairs:
+                    for state in range(rs, re+1):
+                        transcond = self.optimizer.optimize(state_node.transcond)
+                        if isinstance(transcond, DFEvalValue) and transcond.value == 0: continue
+                        active_conditions.append( (state, transcond) )
+        return tuple(active_conditions)
+
+################################################################################
+if __name__ == '__main__':
+    from optparse import OptionParser
+    from pyverilog.definition_analyzer.definition_analyzer import VerilogDefinitionAnalyzer
+    from pyverilog.definition_resolver.definition_resolver import VerilogDefinitionResolver
+    INFO = "Active condition analyzer for Verilog definitions with Pyverilog"
+    VERSION = pyverilog.utils.version.VERSION
+    USAGE = "Usage: python active_analyzer.py -t TOPMODULE file ..."
+
+    def showVersion():
+        print(INFO)
+        print(VERSION)
+        print(USAGE)
+        sys.exit()
+
+    optparser = OptionParser()
+    optparser.add_option("-v","--version",action="store_true",dest="showversion",
+                         default=False,help="Show the version")
+    optparser.add_option("-t","--top",dest="topmodule",
+                         default="TOP",help="Top module, Default=TOP")
+    optparser.add_option("-s","--search",dest="searchtarget",action="append",
+                         default=[],help="Search Target Signal")
+    (options, args) = optparser.parse_args()
+
+    filelist = args
+    if options.showversion:
+        showVersion()
+
+    for f in filelist:
+        if not os.path.exists(f): raise IOError("file not found: " + f)
+
+    if len(filelist) == 0:
+        showVersion()
+
+    verilogdefinitionanalyzer = VerilogDefinitionAnalyzer(filelist, options.topmodule)
+    verilogdefinitionanalyzer.generate()
+
+    directives = verilogdefinitionanalyzer.get_directives()
+    terms = verilogdefinitionanalyzer.getTerms()
+    binddict = verilogdefinitionanalyzer.getBinddict()
+
+    verilogdefinitionresolver = VerilogDefinitionResolver(terms, binddict)
+
+    verilogdefinitionresolver.resolveConstant()
+    resolved_terms = verilogdefinitionresolver.getResolvedTerms()
+    resolved_binddict = verilogdefinitionresolver.getResolvedBinddict()
+    constlist = verilogdefinitionresolver.getConstlist()
+
+    active = VerilogActiveCondition(options.topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist)
+
+    for target in options.searchtarget:
+        signal = util.toTermname(target)
+        active_conditions = active.getActiveConditions( signal )
+
+        #active_conditions = active.getActiveConditions( signal, condition=tree_splitter.active_modify )
+        #active_conditions = active.getActiveConditions( signal, condition=tree_splitter.active_unmodify )
+
+        print('Active Cases: %s' % signal)
+        for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x:str(x[0])):
+            print('FSM: %s' % fsm_sig)
+            for state, active_condition in sorted(active_conditions, key=lambda x:str(x[0])):
+                s = []
+                s.append('state: %d -> ' % state)
+                if active_condition: s.append(active_condition.tocode())
+                else: s.append('empty')
+                print(''.join(s))