Basis gate decomposition success depends on knowing internal implimentation details

[nonhermitian]

What should we add?

Consider the following simple circuit:

qc = QuantumCircuit(1)
qc.y(0)

I should be able to decompose this into the following:

   ┌────────┐┌───┐
q: ┤ Rz(-π) ├┤ X ├
   └────────┘└───┘

However, using the rz and x basis in the transpiler fails:

transpile(qc, basis_gates=['rz', 'x'])

Unable to translate the operations in the circuit: ['y'] to the backend's (or manually specified) target basis: ['reset', 'delay', 'x', 'snapshot', 'rz', 'barrier', 'measure']

In order to work around this, I one needs to know about the internals of how the gate equivalence works. Namely that adding an sx gate that is used as an intermediary will yield the correct decomposition, and the above circuit:

transpile(qc, basis_gates=['rz', 'sx', 'x'])

It would be nice if the success of the decomposition did not rely on understanding internal implementation issues.

[jakelishman]

In principle, the basis translator can do what you're asking, no internal details necessary. The problem is that the standard equivalence library is mostly populated by rules that translate into the [sx, rz, cx], and then conversions between sx and some other bits, and the different rotation axes - they notably don't tend to use the "full" x or z.

Algorithmically all the pieces are in place, we just need to play a bit of whack-a-mole adding some extra equivalences to the standard equivalence library as we find interesting cases. For your specific example, I think adding the three Pauli relations X -> -iYZ etc (or whatever the Levi-Civita ordering is that makes it work) would fix it.

Looking further, it gets pretty interesting/complex when we start talking about the optimisation/resynthesis of 1q/2q blocks. We have a finite number of special-case targets for them, so it's quite easy to come up with awkward limited gate sets for backends that we wouldn't be able to optimise for.

[jakelishman]

Just to illustrate the point a little - the basis translator actually uses the rule Y -> SSHSSH, H -> S Sx S, and S -> U1(pi/2) -> RZ(pi/2) in your working example - we never actually put any S, H or U1 gates on the intermediate circuit, but the decomposition logically goes via them.