projects: hslink-pro: improve CLK clock output accuracy

- in SPI mode, SWD can be adjusted from 80M to 100Khz - in single SPI mode, jtag clk can be adjusted from 80 to 100 khz - remove IO mode
RCSN · Sep 15, 2024 · 6a7db6a · 6a7db6a
1 parent 8cdeb21
commit 6a7db6a
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Showing 2 changed files with 12 additions and 36 deletions.
diff --git a/projects/HSLink-Pro/src/SW_DP/SW_DP.c b/projects/HSLink-Pro/src/SW_DP/SW_DP.c
@@ -1,6 +1,6 @@
 #include "SW_DP.h"
 
-PORT_Mode_t SWD_Port_Mode;
+PORT_Mode_t SWD_Port_Mode = PORT_MODE_SPI;
 
 void PORT_SWD_SETUP(void)
 {

diff --git a/projects/HSLink-Pro/src/dp_common.c b/projects/HSLink-Pro/src/dp_common.c
@@ -9,11 +9,11 @@
 #include "hpm_spi_drv.h"
 
 #define SPI_MAX_SRC_CLOCK 80000000
-#define SPI_MIN_SRC_CLOCK 60000000
-
+#define SPI_MID_SRC_CLOCK 60000000
+#define SPI_MIN_SRC_CLOCK 50000000
 void set_swj_clock_frequency(uint32_t clock)
 {
-    uint8_t div, sclk_div;
+    uint32_t div, sclk_div;
     uint32_t sclk_freq_in_hz;
     sclk_freq_in_hz = clock;
     SPI_Type *spi_base = NULL;
@@ -22,53 +22,29 @@ void set_swj_clock_frequency(uint32_t clock)
     if (BOOST_KEIL_SWD_FREQ == 1) {
         sclk_freq_in_hz *= 10;
     }
-    PORT_Mode_t mode;
     if (DAP_Data.debug_port == DAP_PORT_SWD) {
-        if (sclk_freq_in_hz < 1000000) {
-            mode = PORT_MODE_GPIO;
-        } else {
-            mode = PORT_MODE_SPI;
-        }
-
-        // 判断是否需要切换模式
-        if (SWD_Port_Mode != mode) {
-            SWD_Port_Mode = mode;
-            PORT_SWD_SETUP();
-        }
 
         spi_base = SWD_SPI_BASE;
         clock_name = SWD_SPI_BASE_CLOCK_NAME;
     } else {
-        if (sclk_freq_in_hz < 1000000) {
-            mode = PORT_MODE_GPIO;
-        } else {
-            mode = PORT_MODE_SPI;
-        }
-
-        // 判断是否需要切换模式
-        if (JTAG_Port_Mode != mode) {
-            JTAG_Port_Mode = mode;
-            PORT_JTAG_SETUP();
-        }
-
         spi_base = JTAG_SPI_BASE;
         clock_name = JTAG_SPI_BASE_CLOCK_NAME;
     }
 
-    if (mode == PORT_MODE_GPIO) {
-        Set_Clock_Delay(sclk_freq_in_hz);
-        return;
-    }
-
     sclk_div = ((SPI_MAX_SRC_CLOCK / sclk_freq_in_hz) / 2) - 1; /* SCLK = SPI_SRC_CLOK / ((SCLK_DIV + 1) * 2)*/
     if (sclk_div <= 0xFE) {
         div = 10;
     } else {
+        div = 10;
         src_clock = clk_src_pll0_clk1;                              /* 600M */
-        sclk_div = ((SPI_MIN_SRC_CLOCK / sclk_freq_in_hz) / 2) - 1; /* SCLK = SPI_SRC_CLOK / ((SCLK_DIV + 1) * 2)*/
-        if (sclk_div <= 0xFE) {
+        sclk_div = ((SPI_MID_SRC_CLOCK / sclk_freq_in_hz) / 2) - 1; /* SCLK = SPI_SRC_CLOK / ((SCLK_DIV + 1) * 2)*/
+        if (sclk_div >= 0xFE) {
             div = 10;
-            sclk_div = 0xFE; /* The minimum sclk clock allowed is 117KHz */
+            src_clock = clk_src_pll1_clk2;  /* 500M */
+            sclk_div = ((SPI_MIN_SRC_CLOCK / sclk_freq_in_hz) / 2) - 1;
+            if (sclk_div >= 0xFE) {
+                sclk_div = 0xFE; /* The minimum sclk clock allowed is 98KHz */
+            }
         }
     }
     spi_master_set_sclk_div(spi_base, sclk_div);