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  • Saint Petersburg State University of Telecommunications
  • Saint Petersburg, Russia

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  1. verilog-transceiver verilog-transceiver Public

    Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

    Verilog 3 1

  2. axis-i2c-slave axis-i2c-slave Public

    SystemVerilog 2

  3. fpga-useful-list fpga-useful-list Public

    List of useful materials on FPGA topic

    2

  4. si5340-config-loader si5340-config-loader Public

    Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface

    Verilog 1 1

  5. schoolRISCV schoolRISCV Public

    Forked from zhelnio/schoolRISCV

    CPU microarchitecture, step by step

    Makefile

  6. axis-fir-filter axis-fir-filter Public

    SystemVerilog