wip

RIOT-OS · Feb 10, 2016 · 01acbb0 · 01acbb0
1 parent 436d8f6
commit 01acbb0
Show file tree

Hide file tree

Showing 6 changed files with 352 additions and 754 deletions.
diff --git a/boards/stm32f4discovery/include/periph_conf.h b/boards/stm32f4discovery/include/periph_conf.h
@@ -224,52 +224,28 @@ static const uart_conf_t uart_config[] = {
  * @name SPI configuration
  * @{
  */
-#define SPI_NUMOF           (2U)
-#define SPI_0_EN            1
-#define SPI_1_EN            1
-#define SPI_IRQ_PRIO        1
-
-/* SPI 0 device config */
-#define SPI_0_DEV               SPI1
-#define SPI_0_CLKEN()           (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
-#define SPI_0_CLKDIS()          (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
-#define SPI_0_BUS_DIV           1   /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
-#define SPI_0_IRQ               SPI1_IRQn
-#define SPI_0_IRQ_HANDLER       isr_spi1
-/* SPI 0 pin configuration */
-#define SPI_0_SCK_PORT          GPIOA
-#define SPI_0_SCK_PIN           5
-#define SPI_0_SCK_AF            5
-#define SPI_0_SCK_PORT_CLKEN()  (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
-#define SPI_0_MISO_PORT         GPIOA
-#define SPI_0_MISO_PIN          6
-#define SPI_0_MISO_AF           5
-#define SPI_0_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
-#define SPI_0_MOSI_PORT         GPIOA
-#define SPI_0_MOSI_PIN          7
-#define SPI_0_MOSI_AF           5
-#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
+static const spi_conf_t spi_config[] = {
+    {
+        SPI1,
+        GPIO_PIN(PORT_A, 7),
+        GPIO_PIN(PORT_A, 6),
+        GPIO_PIN(PORT_A, 5),
+        5,
+        BUS_APB2,
+        RCC_APB2ENR_SPI1EN
+    },
+    {
+        SPI2,
+        GPIO_PIN(PORT_B, 15),
+        GPIO_PIN(PORT_B, 14),
+        GPIO_PIN(PORT_B, 13),
+        5,
+        BUS_APB1,
+        RCC_APB1ENR_SPI2EN
+    }
+};
 
-/* SPI 1 device config */
-#define SPI_1_DEV               SPI2
-#define SPI_1_CLKEN()           (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
-#define SPI_1_CLKDIS()          (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
-#define SPI_1_BUS_DIV           0   /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
-#define SPI_1_IRQ               SPI2_IRQn
-#define SPI_1_IRQ_HANDLER       isr_spi2
-/* SPI 1 pin configuration */
-#define SPI_1_SCK_PORT          GPIOB
-#define SPI_1_SCK_PIN           13
-#define SPI_1_SCK_AF            5
-#define SPI_1_SCK_PORT_CLKEN()  (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
-#define SPI_1_MISO_PORT         GPIOB
-#define SPI_1_MISO_PIN          14
-#define SPI_1_MISO_AF           5
-#define SPI_1_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
-#define SPI_1_MOSI_PORT         GPIOB
-#define SPI_1_MOSI_PIN          15
-#define SPI_1_MOSI_AF           5
-#define SPI_1_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
+#define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
 /** @} */
 
 /**

diff --git a/cpu/stm32f4/Makefile.include b/cpu/stm32f4/Makefile.include
@@ -1,6 +1,3 @@
 export CPU_ARCH = cortex-m4f
 
-# use common periph functions
-USEMODULE += periph_common
-
 include $(RIOTCPU)/Makefile.include.cortexm_common
diff --git a/cpu/stm32f4/include/periph_cpu.h b/cpu/stm32f4/include/periph_cpu.h
@@ -25,6 +25,11 @@
 extern "C" {
 #endif
 
+/**
+ * @brief   Length of the CPU_ID in octets
+ */
+#define CPUID_LEN           (12U)
+
 /**
  * @brief   Overwrite the default gpio_t type definition
  * @{
@@ -44,18 +49,17 @@ typedef uint32_t gpio_t;
 #define GPIO_PIN(x, y)      ((GPIOA_BASE + (x << 10)) | y)
 
 /**
- * @brief declare needed generic SPI functions
- * @{
+ * @brief   Override HWSC macro
  */
-#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
-#define PERIPH_SPI_NEEDS_TRANSFER_REG
-#define PERIPH_SPI_NEEDS_TRANSFER_REGS
-/** @} */
+#define SPI_HWCS(x)         (x)
 
-/**
- * @brief   Length of the CPU_ID in octets
+/*
+ * @brief   Peripheral buses
  */
-#define CPUID_LEN           (12U)
+enum {
+    BUS_APB1 = 1,
+    BUS_APB2 = 0
+};
 
 /**
  * @brief   Available ports on the STM32F4 family
@@ -109,6 +113,19 @@ typedef struct {
 } uart_conf_t;
 /** @} */
 
+/**
+ * @brief   Structure for SPI configuration data
+ */
+typedef struct {
+    SPI_TypeDef *dev;       /**< SPI device base register address */
+    gpio_t mosi_pin;        /**< MOSI pin */
+    gpio_t miso_pin;        /**< MISO pin */
+    gpio_t sclk_pin;        /**< SCLK pin */
+    gpio_af_t af;           /**< pin alternate function */
+    uint8_t abpbus;         /**< APB bus, 0 := APB1, 1:= APB2 */
+    uint32_t rccmask;         /**< bit in the RCC peripheral enable register */
+} spi_conf_t;
+
 /**
  * @brief   Configure the alternate function for the given pin
  *