cpu/stm32_common: unify gpio driver

RIOT-OS · Mar 13, 2017 · 7b686b3 · 7b686b3
1 parent 302d5d3
commit 7b686b3
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Showing 24 changed files with 125 additions and 1,345 deletions.
diff --git a/cpu/stm32_common/include/periph_cpu_common.h b/cpu/stm32_common/include/periph_cpu_common.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Freie Universität Berlin
+ *               2017 OTA keys S.A.
  *
  * This file is subject to the terms and conditions of the GNU Lesser
  * General Public License v2.1. See the file LICENSE in the top level
@@ -14,6 +15,7 @@
  * @brief           Shared CPU specific definitions for the STM32 family
  *
  * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author          Vincent Dupont <vincent@otakeys.com>
  */
 
 #ifndef PERIPH_CPU_COMMON_H
@@ -120,11 +122,11 @@ typedef enum {
     GPIO_AF1,               /**< use alternate function 1 */
     GPIO_AF2,               /**< use alternate function 2 */
     GPIO_AF3,               /**< use alternate function 3 */
-#ifndef CPU_FAM_STM32F0
     GPIO_AF4,               /**< use alternate function 4 */
     GPIO_AF5,               /**< use alternate function 5 */
     GPIO_AF6,               /**< use alternate function 6 */
     GPIO_AF7,               /**< use alternate function 7 */
+#ifndef CPU_FAM_STM32F0
     GPIO_AF8,               /**< use alternate function 8 */
     GPIO_AF9,               /**< use alternate function 9 */
     GPIO_AF10,              /**< use alternate function 10 */
@@ -137,6 +139,47 @@ typedef enum {
 #endif
 } gpio_af_t;
 
+#ifndef CPU_FAM_STM32F1
+/**
+ * @brief   Generate GPIO mode bitfields
+ *
+ * We use 5 bit to encode the mode:
+ * - bit 0+1: pin mode (input / output)
+ * - bit 2+3: pull resistor configuration
+ * - bit   4: output type (0: push-pull, 1: open-drain)
+ */
+#define GPIO_MODE(io, pr, ot)   ((io << 0) | (pr << 2) | (ot << 4))
+
+#ifndef DOXYGEN
+/**
+ * @brief   Override GPIO mode options
+ * @{
+ */
+#define HAVE_GPIO_MODE_T
+typedef enum {
+    GPIO_IN    = GPIO_MODE(0, 0, 0),    /**< input w/o pull R */
+    GPIO_IN_PD = GPIO_MODE(0, 2, 0),    /**< input with pull-down */
+    GPIO_IN_PU = GPIO_MODE(0, 1, 0),    /**< input with pull-up */
+    GPIO_OUT   = GPIO_MODE(1, 0, 0),    /**< push-pull output */
+    GPIO_OD    = GPIO_MODE(1, 0, 1),    /**< open-drain w/o pull R */
+    GPIO_OD_PU = GPIO_MODE(1, 1, 1)     /**< open-drain with pull-up */
+} gpio_mode_t;
+/** @} */
+
+/**
+ * @brief   Override flank configuration values
+ * @{
+ */
+#define HAVE_GPIO_FLANK_T
+typedef enum {
+    GPIO_RISING = 1,        /**< emit interrupt on rising flank */
+    GPIO_FALLING = 2,       /**< emit interrupt on falling flank */
+    GPIO_BOTH = 3           /**< emit interrupt on both flanks */
+} gpio_flank_t;
+/** @} */
+#endif /* ndef DOXYGEN */
+#endif /* ndef CPU_FAM_STM32F1 */
+
 /**
  * @brief   Timer configuration
  */

diff --git a/cpu/stm32f0/periph/gpio.c → cpu/stm32_common/periph/gpio.c b/cpu/stm32f0/periph/gpio.c → cpu/stm32_common/periph/gpio.c
@@ -1,23 +1,32 @@
 /*
- * Copyright (C) 2014 Freie Universität Berlin
+ * Copyright (C) 2014-2015 Freie Universität Berlin
+ *               2015 Hamburg University of Applied Sciences
+ *               2017 Inria
+ *               2017 OTA keys S.A.
  *
  * This file is subject to the terms and conditions of the GNU Lesser General
  * Public License v2.1. See the file LICENSE in the top level directory for more
  * details.
  */
 
 /**
- * @ingroup     cpu_stm32f0
+ * @ingroup     cpu_stm32_common
  * @{
  *
  * @file
  * @brief       Low-level GPIO driver implementation
  *
  * @author      Hauke Petersen <mail@haukepetersen.de>
+ * @author      Fabian Nack <nack@inf.fu-berlin.de>
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author      Katja Kirstein <katja.kirstein@haw-hamburg.de>
+ * @author      Vincent Dupont <vincent@otakeys.com>
  *
  * @}
  */
 
+#ifndef CPU_FAM_STM32F1
+
 #include "cpu.h"
 #include "periph/gpio.h"
 #include "periph_conf.h"
@@ -65,7 +74,13 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
     int pin_num = _pin_num(pin);
 
     /* enable clock */
+#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1)
     periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
+#elif defined (CPU_FAM_STM32L0)
+    periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
+#else
+    periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
+#endif
 
     /* set mode */
     port->MODER &= ~(0x3 << (2 * pin_num));
@@ -78,7 +93,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
     port->OTYPER |=  (((mode >> 4) & 0x1) << pin_num);
     /* finally set pin speed to maximum and reset output */
     port->OSPEEDR |= (3 << (2 * pin_num));
-    port->BRR = (1 << pin_num);
+    port->BSRR = (1 << (pin_num + 16));
 
     return 0;
 }
@@ -94,12 +109,17 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     isr_ctx[pin_num].arg = arg;
 
     /* enable clock of the SYSCFG module for EXTI configuration */
+#ifdef CPU_FAN_STM32F0
     periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
+#else
+    periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
+#endif
 
     /* initialize pin as input */
     gpio_init(pin, mode);
 
     /* enable global pin interrupt */
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0)
     if (pin_num < 2) {
         NVIC_EnableIRQ(EXTI0_1_IRQn);
     }
@@ -109,6 +129,17 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     else {
         NVIC_EnableIRQ(EXTI4_15_IRQn);
     }
+#else
+    if (pin_num < 5) {
+        NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
+    }
+    else if (pin_num < 10) {
+        NVIC_EnableIRQ(EXTI9_5_IRQn);
+    }
+    else {
+        NVIC_EnableIRQ(EXTI15_10_IRQn);
+    }
+#endif
     /* configure the active flank */
     EXTI->RTSR &= ~(1 << pin_num);
     EXTI->RTSR |=  ((flank & 0x1) << pin_num);
@@ -143,7 +174,13 @@ void gpio_init_analog(gpio_t pin)
 {
     /* enable clock, needed as this function can be used without calling
      * gpio_init first */
+#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1)
     periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
+#elif defined (CPU_FAM_STM32L0)
+    periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
+#else
+    periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
+#endif
     /* set to analog mode */
     _port(pin)->MODER |= (0x3 << (2 * _pin_num(pin)));
 }
@@ -175,24 +212,24 @@ void gpio_set(gpio_t pin)
 
 void gpio_clear(gpio_t pin)
 {
-    _port(pin)->BRR = (1 << _pin_num(pin));
+    _port(pin)->BSRR = (1 << (_pin_num(pin) + 16));
 }
 
 void gpio_toggle(gpio_t pin)
 {
     if (gpio_read(pin)) {
-        _port(pin)->BRR = (1 << _pin_num(pin));
+        gpio_clear(pin);
     } else {
-        _port(pin)->BSRR = (1 << _pin_num(pin));
+        gpio_set(pin);
     }
 }
 
 void gpio_write(gpio_t pin, int value)
 {
     if (value) {
-        _port(pin)->BSRR = (1 << _pin_num(pin));
+        gpio_set(pin);
     } else {
-        _port(pin)->BRR = (1 << _pin_num(pin));
+        gpio_clear(pin);
     }
 }
 
@@ -208,3 +245,7 @@ void isr_exti(void)
     }
     cortexm_isr_end();
 }
+
+#else
+typedef int dont_be_pedantic;
+#endif
diff --git a/cpu/stm32f0/include/periph_cpu.h b/cpu/stm32f0/include/periph_cpu.h
@@ -25,45 +25,6 @@
 extern "C" {
 #endif
 
-/**
- * @brief   Generate GPIO mode bitfields
- *
- * We use 5 bit to encode the mode:
- * - bit 0+1: pin mode (input / output)
- * - bit 2+3: pull resistor configuration
- * - bit   4: output type (0: push-pull, 1: open-drain)
- */
-#define GPIO_MODE(io, pr, ot)   ((io << 0) | (pr << 2) | (ot << 4))
-
-#ifndef DOXYGEN
-/**
- * @brief   Override GPIO mode options
- * @{
- */
-#define HAVE_GPIO_MODE_T
-typedef enum {
-    GPIO_IN    = GPIO_MODE(0, 0, 0),    /**< input w/o pull R */
-    GPIO_IN_PD = GPIO_MODE(0, 2, 0),    /**< input with pull-down */
-    GPIO_IN_PU = GPIO_MODE(0, 1, 0),    /**< input with pull-up */
-    GPIO_OUT   = GPIO_MODE(1, 0, 0),    /**< push-pull output */
-    GPIO_OD    = GPIO_MODE(1, 0, 1),    /**< open-drain w/o pull R */
-    GPIO_OD_PU = GPIO_MODE(1, 1, 1)     /**< open-drain with pull-up */
-} gpio_mode_t;
-/** @} */
-
-/**
- * @brief   Override flank configuration values
- * @{
- */
-#define HAVE_GPIO_FLANK_T
-typedef enum {
-    GPIO_RISING = 1,        /**< emit interrupt on rising flank */
-    GPIO_FALLING = 2,       /**< emit interrupt on falling flank */
-    GPIO_BOTH = 3           /**< emit interrupt on both flanks */
-} gpio_flank_t;
-/** @} */
-#endif /* ndef DOXYGEN */
-
 /**
  * @brief   Available ports on the STM32F0 family
  */
@@ -72,6 +33,7 @@ enum {
     PORT_B = 1,             /**< port B */
     PORT_C = 2,             /**< port C */
     PORT_D = 3,             /**< port D */
+    PORT_E = 4,             /**< port E */
     PORT_F = 5,             /**< port F */
 };
 

diff --git a/cpu/stm32f2/include/periph_cpu.h b/cpu/stm32f2/include/periph_cpu.h
@@ -27,31 +27,6 @@
 extern "C" {
 #endif
 
-/**
- * @brief   Generate GPIO mode bitfields
- *
- * We use 5 bit to encode the mode:
- * - bit 0+1: pin mode (input / output)
- * - bit 2+3: pull resistor configuration
- * - bit   4: output type (0: push-pull, 1: open-drain)
- */
-#define GPIO_MODE(io, pr, ot)   ((io << 0) | (pr << 2) | (ot << 4))
-
-/**
- * @brief   Override GPIO mode options
- * @{
- */
-#define HAVE_GPIO_MODE_T
-typedef enum {
-    GPIO_IN    = GPIO_MODE(0, 0, 0),    /**< input w/o pull R */
-    GPIO_IN_PD = GPIO_MODE(0, 2, 0),    /**< input with pull-down */
-    GPIO_IN_PU = GPIO_MODE(0, 1, 0),    /**< input with pull-up */
-    GPIO_OUT   = GPIO_MODE(1, 0, 0),    /**< push-pull output */
-    GPIO_OD    = GPIO_MODE(1, 0, 1),    /**< open-drain w/o pull R */
-    GPIO_OD_PU = GPIO_MODE(1, 1, 1)     /**< open-drain with pull-up */
-} gpio_mode_t;
-/** @} */
-
 /**
  * @brief   Available ports on the STM32F2 family
  */