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stm32/can: add option to enable deep-sleep per device #14911

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merged 2 commits into from
Feb 22, 2021
Merged

stm32/can: add option to enable deep-sleep per device #14911

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eb0f658
stm32/can: add option to enable deep-sleep per device
Sep 13, 2019
2edf37e
cpu/stm32/can: use en_deep_sleep_wake_up by default
Feb 2, 2021
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3 changes: 3 additions & 0 deletions cpu/stm32/include/can_params.h
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,7 @@ static const can_conf_t candev_conf[] = {
.rx1_irqn = CAN1_RX1_IRQn,
.sce_irqn = CAN1_SCE_IRQn,
#endif
.en_deep_sleep_wake_up = true,
.ttcm = 0,
.abom = 1,
.awum = 1,
Expand All @@ -85,6 +86,7 @@ static const can_conf_t candev_conf[] = {
#ifndef CPU_FAM_STM32F1
.af = GPIO_AF9,
#endif
.en_deep_sleep_wake_up = true,
.tx_irqn = CAN2_TX_IRQn,
.rx0_irqn = CAN2_RX0_IRQn,
.rx1_irqn = CAN2_RX1_IRQn,
Expand All @@ -108,6 +110,7 @@ static const can_conf_t candev_conf[] = {
.rx_pin = GPIO_PIN(PORT_B, 3),
.tx_pin = GPIO_PIN(PORT_B, 4),
.af = GPIO_AF11,
.en_deep_sleep_wake_up = true,
.tx_irqn = CAN3_TX_IRQn,
.rx0_irqn = CAN3_RX0_IRQn,
.rx1_irqn = CAN3_RX1_IRQn,
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1 change: 1 addition & 0 deletions cpu/stm32/include/candev_stm32.h
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Expand Up @@ -100,6 +100,7 @@ typedef struct {
#ifndef CPU_FAM_STM32F1
gpio_af_t af; /**< Alternate pin function to use */
#endif
bool en_deep_sleep_wake_up; /**< Enable deep-sleep wake-up interrupt */
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Why not extend the bit field below? (line 130)

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The bitfield was using uint8_t as the base type and there were already eight bits in it. Also, the bits in the bit field correspond to a setting in the config register.

#if CANDEV_STM32_CHAN_NUMOF > 1 || defined(DOXYGEN)
CAN_TypeDef *can_master; /**< Master CAN device */
uint32_t master_rcc_mask; /**< Master device RCC mask */
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36 changes: 25 additions & 11 deletions cpu/stm32/periph/can.c
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Original file line number Diff line number Diff line change
Expand Up @@ -644,8 +644,10 @@ static void turn_off(can_t *dev)
#endif
}
_status[chan] = STATUS_SLEEP;
periph_clk_dis(APB1, dev->conf->rcc_mask);
enable_int(dev, 0);
if (dev->conf->en_deep_sleep_wake_up) {
periph_clk_dis(APB1, dev->conf->rcc_mask);
enable_int(dev, 0);
}
}
}
else {
Expand All @@ -658,20 +660,26 @@ static void turn_off(can_t *dev)
#endif
/* Fall through */
case STATUS_NOT_USED:
periph_clk_dis(APB1, dev->conf->master_rcc_mask);
if (dev->conf->en_deep_sleep_wake_up) {
periph_clk_dis(APB1, dev->conf->master_rcc_mask);
}
break;
}
periph_clk_dis(APB1, dev->conf->rcc_mask);
if (dev->conf->en_deep_sleep_wake_up) {
periph_clk_dis(APB1, dev->conf->rcc_mask);
}
if (_status[get_channel(dev->conf->can)] != STATUS_SLEEP) {
#ifdef STM32_PM_STOP
pm_unblock(STM32_PM_STOP);
#endif
}
_status[get_channel(dev->conf->can)] = STATUS_SLEEP;
if (_status[master_chan] == STATUS_SLEEP) {
enable_int(dev, 1);
if (dev->conf->en_deep_sleep_wake_up) {
if (_status[master_chan] == STATUS_SLEEP) {
enable_int(dev, 1);
}
enable_int(dev, 0);
}
enable_int(dev, 0);
}
#else
if (_status[get_channel(dev->conf->can)] != STATUS_SLEEP) {
Expand All @@ -680,8 +688,10 @@ static void turn_off(can_t *dev)
#endif
}
_status[get_channel(dev->conf->can)] = STATUS_SLEEP;
periph_clk_dis(APB1, dev->conf->rcc_mask);
gpio_init_int(dev->rx_pin, GPIO_IN, GPIO_FALLING, _wkup_cb, dev);
if (dev->conf->en_deep_sleep_wake_up) {
periph_clk_dis(APB1, dev->conf->rcc_mask);
gpio_init_int(dev->rx_pin, GPIO_IN, GPIO_FALLING, _wkup_cb, dev);
}
#endif
irq_restore(irq);
}
Expand All @@ -697,7 +707,9 @@ static void turn_on(can_t *dev)
switch (_status[master_chan]) {
case STATUS_SLEEP:
_status[master_chan] = STATUS_READY_FOR_SLEEP;
disable_int(dev, 1);
if (dev->conf->en_deep_sleep_wake_up) {
disable_int(dev, 1);
}
#ifdef STM32_PM_STOP
pm_block(STM32_PM_STOP);
#endif
Expand All @@ -712,7 +724,9 @@ static void turn_on(can_t *dev)
#ifdef STM32_PM_STOP
pm_block(STM32_PM_STOP);
#endif
disable_int(dev, 0);
if (dev->conf->en_deep_sleep_wake_up) {
disable_int(dev, 0);
}
periph_clk_en(APB1, dev->conf->rcc_mask);
}
_status[get_channel(dev->conf->can)] = STATUS_ON;
Expand Down