fix Clang Format issue

ROCm · Oct 9, 2023 · c34c72a · c34c72a
1 parent 505f6ab
commit c34c72a
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/kernels/gpu_reference_kernel/naive_conv.cpp b/src/kernels/gpu_reference_kernel/naive_conv.cpp
@@ -128,7 +128,7 @@ inline __device__ __host__ int8_t cast_to(const int32_t& val)
 ///
 /// - strides here are stored right to left, i.e., for NHWC, stride for N is
 /// at index 3 while stride for C is at index 0. This is different from how the
-/// tensor descriptors store strides, which is always NCHW order, left-to-right. 
+/// tensor descriptors store strides, which is always NCHW order, left-to-right.
 
 template <bool ASSUME_PACKED, typename src_data_t, typename acc_data_t, typename dst_data_t>
 inline __device__ void naive_conv_fwd_nchw(const src_data_t* __restrict__ p_in,

diff --git a/src/solver/conv_direct_naive_conv.cpp b/src/solver/conv_direct_naive_conv.cpp
@@ -113,7 +113,7 @@ std::string ConvDirectNaiveConvKernelName(const ProblemDescription& problem)
     std::ostringstream kernel_name;
 
     /// \todo remove packed reference convolution kernels --amberhassaan
-#ifndef NDEBUG// enable in debug mode only
+#ifndef NDEBUG // enable in debug mode only
     if(miopen::IsEnabled(MIOPEN_DEBUG_CONV_DIRECT_NAIVE_USE_PACKED_KERNELS()))
     {
         kernel_name << "naive_conv_packed_";