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Thomas Roehl edited this page Nov 16, 2020 · 2 revisions

Architecture specific notes for Intel® Icelake

Performance groups

Intel® Icelake Performance groups

Events

The input file for the events on Intel® Icelake can be found here.

Counters

Core-local counters

Fixed-purpose counters

Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose counters. Each can measure only one specific event.

Counters
Counter name Event name
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
FIXC3 TOPDOWN_SLOTS
Available Options
Option Argument Description Comment
anythread N Set bit 2+(index*4) in config register
kernel N Set bit (index*4) in config register

Performance metric counters

With the Intel® Icelake microarchitecture a new class of core-local counters was introduced, the so-called perf-metrics. The reflect the first level of the Top-down Microarchitecture Analysis tree.

Counters
Counter name Event name
TMA0 RETIRING
TMA1 BAD_SPECULATION
TMA2 FRONTEND_BOUND
TMA3 BACKEND_BOUND

The events return the fraction of slots used by the event.

General-purpose counters

The Intel® Icelake microarchitecture provides 4 general-purpose counters consisting of a config and a counter register.

Counters
Counter name Event name
PMC0 *
PMC1 *
PMC2 *
PMC3 *
PMC4 * (only available without HyperThreading)
PMC5 * (only available without HyperThreading)
PMC6 * (only available without HyperThreading)
PMC7 * (only available without HyperThreading)
Available Options
Option Argument Description Comment
edgedetect N Set bit 18 in config register
kernel N Set bit 17 in config register
anythread N Set bit 21 in config register The anythread option is deprecated! Please check the documentation how to use it on Icelake
threshold 8 bit hex value Set bits 24-31 in config register
invert N Set bit 23 in config register
in_transaction N Set bit 32 in config register Only available if Intel® Transactional Synchronization Extensions are available
in_transaction_aborted N Set bit 33 in config register Only counter PMC2 and only if Intel® Transactional Synchronization Extensions are available

Thermal counter

The Intel® Icelake microarchitecture provides one register for the current core temperature.

Counters
Counter name Event name
TMP0 TEMP_CORE

Core voltage counter

The Intel® Icelake microarchitecture provides one register for the current core voltage.

Counters
Counter name Event name
VTG0 VOLTAGE_CORE

Socket-wide counters

Energy counters

The Intel® Icelake microarchitecture provides measurements of the current energy consumption through the RAPL interface.

Counters
Counter name Event name
PWR0 PWR_PKG_ENERGY
PWR1 PWR_PP0_ENERGY
PWR2 PWR_PP1_ENERGY
PWR3 PWR_DRAM_ENERGY
PWR4 PWR_PLATFORM_ENERGY

Uncore management fixed-purpose counter

The Intel® Icelake microarchitecture provides measurements of the management box in the uncore.
The single fixed-purpose counter counts the clock frequency of the clock source of the uncore. The uncore management performance counters are exposed to the operating system through the MSR interface. The name UBOX originates from the Nehalem EX uncore monitoring.

Counter
Counter name Event name
UBOXFIX UNCORE_CLOCK

Uncore management general-purpose counters

The Intel® Icelake microarchitecture provides measurements of the management box in the uncore.
The uncore management performance counters are exposed to the operating system through the MSR interface. The name UBOX originates from the Nehalem EX uncore monitoring.

Counter
Counter name Event name
UBOX0 *
UBOX1 *

Last Level cache counters

The Intel® Icelake microarchitecture provides measurements of the LLC coherency engine in the uncore.
The LLC hardware performance counters are exposed to the operating system through the MSR interface. The maximal amount of supported coherency engines for the Intel® Icelake microarchitecture is 8. It may be possible that your systems does not have all CBOXes, LIKWID will skip the unavailable ones in the setup phase. The name CBOX originates from the Nehalem EX uncore monitoring.

Counters
Counter name Event name
CBOX<0-7>C0 *
CBOX<0-7>C1 *
Available Options
Option Argument Operation Comment
edgedetect N Set bit 18 in config register
invert N Set bit 23 in config register
threshold 5 bit hex value Set bits 24-28 in config register

Memory controller counters

The Intel® Icelake microarchitecture provides measurements of the memory controllers in the uncore
The memory controller is exposed through MMIO and provides three free-running counters.

Counters
Counter name  Event name
MBOX0C0 IO_REQUESTS
MBOX0C1 DRAM_READS
MBOX0C2 DRAM_WRITES
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