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128 changes: 128 additions & 0 deletions Assessments/Lab 2 Assessment/Lab_2_Assessment.asm.rpt
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Assembler report for Lab_2_Assessment
Wed Feb 23 14:50:03 2022
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.sof
6. Assembler Device Options: C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.pof
7. Assembler Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.



+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Feb 23 14:50:03 2022 ;
; Revision Name ; Lab_2_Assessment ;
; Top-level Entity Name ; Lab_2_Assessment ;
; Family ; FLEX10KE ;
; Device ; EPF10K30ETC144-1 ;
+-----------------------+---------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Low-voltage mode ; On ; On ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Auto-increment JTAG user code for multiple configuration devices ; On ; On ;
; Disable CONF_DONE and nSTATUS pull-ups on configuration device ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+


+-------------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------------------------------------------------------+
; File Name ;
+-------------------------------------------------------------------------------------------------+
; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.sof ;
; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.pof ;
+-------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.sof ;
+----------------+----------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------------------------------------------------------+
; Device ; EPF10K30ETC144-1 ;
; JTAG usercode ; 0x0000007F ;
; Checksum ; 0x0000C455 ;
+----------------+----------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.pof ;
+--------------------+------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+--------------------+------------------------------------------------------------------------------------------------------+
; Device ; EPC2 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x02581423 ;
; Compression Ratio ; 1 ;
+--------------------+------------------------------------------------------------------------------------------------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
Info: Processing started: Wed Feb 23 14:50:03 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 198 megabytes
Info: Processing ended: Wed Feb 23 14:50:03 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00


1 change: 1 addition & 0 deletions Assessments/Lab 2 Assessment/Lab_2_Assessment.done
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Wed Feb 23 14:55:07 2022
119 changes: 119 additions & 0 deletions Assessments/Lab 2 Assessment/Lab_2_Assessment.eda.rpt
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EDA Netlist Writer report for Lab_2_Assessment
Wed Feb 23 14:50:06 2022
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. Timing Analysis Settings
6. Timing Analysis Generated Files
7. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.



+------------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+--------------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Feb 23 14:50:06 2022 ;
; Revision Name ; Lab_2_Assessment ;
; Top-level Entity Name ; Lab_2_Assessment ;
; Family ; FLEX10KE ;
; Simulation Files Creation ; Successful ;
; Timing Analysis Files Creation ; Successful ;
+--------------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+--------------------------------------------------------------------------------------------+--------------------+
; Option ; Setting ;
+--------------------------------------------------------------------------------------------+--------------------+
; Tool Name ; Custom Verilog HDL ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
+--------------------------------------------------------------------------------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+---------------------------------------------------------------------------------------------------------------------+
; Generated Files ;
+---------------------------------------------------------------------------------------------------------------------+
; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/simulation/custom/Lab_2_Assessment.vo ;
; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/simulation/custom/Lab_2_Assessment_v.sdo ;
+---------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------+
; Timing Analysis Settings ;
+-------------------------------------+--------------------+
; Option ; Setting ;
+-------------------------------------+--------------------+
; Tool Name ; Custom Verilog HDL ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
+-------------------------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Timing Analysis Generated Files ;
+-----------------------------------------------------------------------------------------------------------------+
; Generated Files ;
+-----------------------------------------------------------------------------------------------------------------+
; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/timing/custom/Lab_2_Assessment.vo ;
; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/timing/custom/Lab_2_Assessment_v.sdo ;
+-----------------------------------------------------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
Info: Processing started: Wed Feb 23 14:50:06 2022
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment
Info: Generated files "Lab_2_Assessment.vo" and "Lab_2_Assessment_v.sdo" in directory "C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/simulation/custom/" for EDA simulation tool
Info: Generated files "Lab_2_Assessment.vo" and "Lab_2_Assessment_v.sdo" in directory "C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/timing/custom/" for EDA timing analysis tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 156 megabytes
Info: Processing ended: Wed Feb 23 14:50:06 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00


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