Move RiscV tests

suite/cstest/include/test_detail.h

@@ -12,6 +12,7 @@
 #include "test_detail_aarch64.h"
 #include "test_detail_arm.h"
 #include "test_detail_ppc.h"
+#include "test_detail_riscv.h"
 #include "test_detail_tricore.h"
 #include "test_detail_systemz.h"
 #include "test_detail_sh.h"
@@ -21,6 +22,7 @@
 #include "test_detail_hppa.h"
 #include "test_detail_xcore.h"
 #include "test_detail_mips.h"
+#include "test_detail_riscv.h"
 #include "test_compare.h"
 #include <capstone/capstone.h>
 #include <cyaml/cyaml.h>
@@ -40,16 +42,15 @@ typedef struct {
 	TestDetailXCore *xcore;
 	TestDetailSH *sh;
 	TestDetailMips *mips;
+	TestDetailRISCV *riscv;
 	// cs_x86_test x86;
 	// cs_m68k_test m68k;
-	// cs_mips_test mips;
 	// cs_tms320c64x_test tms320c64x;
 	// cs_m680x_test m680x;
 	// cs_evm_test evm;
 	// cs_mos65xx_test mos65xx;
 	// cs_wasm_test wasm;
 	// cs_riscv_test riscv;
-	// cs_sh_test sh;
 	// cs_loongarch_test loongarch;
 
 	char **regs_read;
@@ -105,6 +106,9 @@ static const cyaml_schema_field_t test_detail_mapping_schema[] = {
 	CYAML_FIELD_MAPPING_PTR(
 		"mips", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
 		mips, test_detail_mips_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"riscv", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		riscv, test_detail_riscv_mapping_schema),
 	CYAML_FIELD_SEQUENCE("regs_read",
 			     CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
 			     TestDetail, regs_read, &reg_group_schema, 0, 255),

suite/cstest/include/test_detail_riscv.h

@@ -0,0 +1,66 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_RISCV_H
+#define TEST_DETAIL_RISCV_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	uint64_t imm;
+	char *mem_base;
+	int64_t mem_disp;
+} TestDetailRISCVOp;
+
+static const cyaml_schema_field_t test_detail_riscv_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailRISCVOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailRISCVOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailRISCVOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailRISCVOp, imm),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailRISCVOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailRISCVOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_riscv_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailRISCVOp,
+			    test_detail_riscv_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailRISCVOp **operands;
+	uint32_t operands_count;
+} TestDetailRISCV;
+
+static const cyaml_schema_field_t test_detail_riscv_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailRISCV, operands, &test_detail_riscv_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailRISCV *test_detail_riscv_new();
+TestDetailRISCV *test_detail_riscv_clone(const TestDetailRISCV *detail);
+void test_detail_riscv_free(TestDetailRISCV *detail);
+
+TestDetailRISCVOp *test_detail_riscv_op_new();
+TestDetailRISCVOp *test_detail_riscv_op_clone(const TestDetailRISCVOp *detail);
+void test_detail_riscv_op_free(TestDetailRISCVOp *detail);
+
+bool test_expected_riscv(csh *handle, const cs_riscv *actual,
+		       const TestDetailRISCV *expected);
+
+#endif // TEST_DETAIL_RISCV_H

suite/cstest/include/test_mapping.h

@@ -637,6 +637,23 @@ static const cs_enum_id_map cs_enum_map[] = {
 	{ .str = "PPC_PRED_Z_MINUS", .val = PPC_PRED_Z_MINUS },
 	{ .str = "PPC_PRED_Z_PLUS", .val = PPC_PRED_Z_PLUS },
 	{ .str = "PPC_PRED_Z_RESERVED", .val = PPC_PRED_Z_RESERVED },
+	{ .str = "RISCV_GRP_BRANCH_RELATIVE", .val = RISCV_GRP_BRANCH_RELATIVE },
+	{ .str = "RISCV_GRP_CALL", .val = RISCV_GRP_CALL },
+	{ .str = "RISCV_GRP_HASSTDEXTA", .val = RISCV_GRP_HASSTDEXTA },
+	{ .str = "RISCV_GRP_HASSTDEXTC", .val = RISCV_GRP_HASSTDEXTC },
+	{ .str = "RISCV_GRP_HASSTDEXTD", .val = RISCV_GRP_HASSTDEXTD },
+	{ .str = "RISCV_GRP_HASSTDEXTF", .val = RISCV_GRP_HASSTDEXTF },
+	{ .str = "RISCV_GRP_HASSTDEXTM", .val = RISCV_GRP_HASSTDEXTM },
+	{ .str = "RISCV_GRP_INT", .val = RISCV_GRP_INT },
+	{ .str = "RISCV_GRP_IRET", .val = RISCV_GRP_IRET },
+	{ .str = "RISCV_GRP_ISRV32", .val = RISCV_GRP_ISRV32 },
+	{ .str = "RISCV_GRP_ISRV64", .val = RISCV_GRP_ISRV64 },
+	{ .str = "RISCV_GRP_JUMP", .val = RISCV_GRP_JUMP },
+	{ .str = "RISCV_GRP_PRIVILEGE", .val = RISCV_GRP_PRIVILEGE },
+	{ .str = "RISCV_GRP_RET", .val = RISCV_GRP_RET },
+	{ .str = "RISCV_OP_IMM", .val = RISCV_OP_IMM },
+	{ .str = "RISCV_OP_MEM", .val = RISCV_OP_MEM },
+	{ .str = "RISCV_OP_REG", .val = RISCV_OP_REG },
 	{ .str = "SH_GRP_BRANCH_RELATIVE", .val = SH_GRP_BRANCH_RELATIVE },
 	{ .str = "SH_GRP_CALL", .val = SH_GRP_CALL },
 	{ .str = "SH_GRP_INT", .val = SH_GRP_INT },

suite/cstest/src/test_detail.c

@@ -82,6 +82,9 @@ TestDetail *test_detail_clone(TestDetail *detail)
 	if (detail->mips) {
 		clone->mips = test_detail_mips_clone(detail->mips);
 	}
+	if (detail->riscv) {
+		clone->riscv = test_detail_riscv_clone(detail->riscv);
+	}
 
 	return clone;
 }
@@ -143,6 +146,9 @@ void test_detail_free(TestDetail *detail)
 	if (detail->mips) {
 		test_detail_mips_free(detail->mips);
 	}
+	if (detail->riscv) {
+		test_detail_riscv_free(detail->riscv);
+	}
 
 	cs_mem_free(detail);
 }
@@ -230,5 +236,9 @@ bool test_expected_detail(csh *handle, const cs_insn *insn,
 		return test_expected_mips(handle, &actual->mips,
 					     expected->mips);
 	}
+	if (expected->riscv) {
+		return test_expected_riscv(handle, &actual->riscv,
+					     expected->riscv);
+	}
 	return true;
 }

suite/cstest/src/test_detail_riscv.c

@@ -0,0 +1,107 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_riscv.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailRISCV *test_detail_riscv_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailRISCV), 1);
+}
+
+void test_detail_riscv_free(TestDetailRISCV *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_riscv_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailRISCV *test_detail_riscv_clone(const TestDetailRISCV *detail)
+{
+	TestDetailRISCV *clone = test_detail_riscv_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailRISCVOp),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_riscv_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailRISCVOp *test_detail_riscv_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailRISCVOp), 1);
+}
+
+TestDetailRISCVOp *test_detail_riscv_op_clone(const TestDetailRISCVOp *op)
+{
+	TestDetailRISCVOp *clone = test_detail_riscv_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_riscv_op_free(TestDetailRISCVOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op);
+}
+
+bool test_expected_riscv(csh *handle, const cs_riscv *actual,
+		       const TestDetailRISCV *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_riscv_op *op = &actual->operands[i];
+		TestDetailRISCVOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"sh op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case RISCV_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case RISCV_OP_IMM:
+			compare_uint64_ret(op->imm, eop->imm, false);
+			break;
+		case RISCV_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_int64_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}