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Move instruction alias description to the top
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Rot127 committed Sep 9, 2024
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Expand Up @@ -98,6 +98,74 @@ Nonetheless, we hope this additional information is useful to you.
- Coverity code scanning workflow added and all reported bugs fixed.
- `clang-tidy` workflow added. All reported defects were fixed.

### Instruction Alias

Instruction alias are now properly separated from real instructions.

The `cs_insn->is_alias` flag is set, if the decoded instruction is an alias.

The real instruction `id` is still set in `cs_insn->id`.
The alias `id` is set in `cs_insn->alias_id`.

You can use as `cs_insn_name()` to retrieve the real and the alias name.

Additionally, you can now choose between the alias details and the real details.

If you always want the real instruction detail decoded (also for alias instructions),
you can enable the option with
```
cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL | CS_OPT_ON);
```

For the `cstool` you can enable it with the `-r` flag.

Without `-r` you get the `alias` operand set, _if_ the instruction is an alias.
This is the default behavior:

```
./cstool -d ppc32be 7a8a2000
0 7a 8a 20 00 rotldi r10, r20, 4
ID: 867 (rldicl)
Is alias: 1828 (rotldi) with ALIAS operand set
op_count: 3
operands[0].type: REG = r10
operands[0].access: WRITE
operands[1].type: REG = r20
operands[1].access: READ
operands[2].type: IMM = 0x4
operands[2].access: READ
```

If `-r` is set, you got the real operands. Even if the decoded instruction is an alias:

```
./cstool -d ppc32be 7a8a2000
0 7a 8a 20 00 rotldi r10, r20, 4
ID: 867 (rldicl)
Is alias: 1828 (rotldi) with REAL operand set
op_count: 4
operands[0].type: REG = r10
operands[0].access: WRITE
operands[1].type: REG = r20
operands[1].access: READ
operands[2].type: IMM = 0x4
operands[2].access: READ
operands[3].type: IMM = 0x0
operands[3].access: READ
```

**Note about alias as part of real instruction enum.**

LLVM defines some alias instructions as real instructions.
This is why you will still find alias instructions being listed in the instruction `enum`.
This happens due to some LLVM specific edge cases.

Nonetheless, an alias should never be **decoded** as real instruction.

If you find an alias which is decoded as a real instruction, please let us know.
Such an instruction is ill-defined in LLVM and should be fixed upstream.

## Breaking changes

**All `auto-sync` architectures**
Expand Down Expand Up @@ -254,71 +322,3 @@ Please note though, `writeback` registers are correctly added to the `regs_write

These issues will be addressed in the next releases. For a more detailed descriptions see: https://github.com/capstone-engine/capstone/issues/2472#issuecomment-2335226281 (starting at "eor and the others").


### Instruction Alias

Instruction alias are now properly separated from real instructions.

The `cs_insn->is_alias` flag is set, if the decoded instruction is an alias.

The real instruction `id` is still set in `cs_insn->id`.
The alias `id` is set in `cs_insn->alias_id`.

You can use as `cs_insn_name()` to retrieve the real and the alias name.

Additionally, you can now choose between the alias details and the real details.

If you always want the real instruction detail decoded (also for alias instructions),
you can enable the option with
```
cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL | CS_OPT_ON);
```

For the `cstool` you can enable it with the `-r` flag.

Without `-r` you get the `alias` operand set, _if_ the instruction is an alias.
This is the default behavior:

```
./cstool -d ppc32be 7a8a2000
0 7a 8a 20 00 rotldi r10, r20, 4
ID: 867 (rldicl)
Is alias: 1828 (rotldi) with ALIAS operand set
op_count: 3
operands[0].type: REG = r10
operands[0].access: WRITE
operands[1].type: REG = r20
operands[1].access: READ
operands[2].type: IMM = 0x4
operands[2].access: READ
```

If `-r` is set, you got the real operands. Even if the decoded instruction is an alias:

```
./cstool -d ppc32be 7a8a2000
0 7a 8a 20 00 rotldi r10, r20, 4
ID: 867 (rldicl)
Is alias: 1828 (rotldi) with REAL operand set
op_count: 4
operands[0].type: REG = r10
operands[0].access: WRITE
operands[1].type: REG = r20
operands[1].access: READ
operands[2].type: IMM = 0x4
operands[2].access: READ
operands[3].type: IMM = 0x0
operands[3].access: READ
```

**Note about alias as part of real instruction enum.**

LLVM defines some alias instructions as real instructions.
This is why you will still find alias instructions being listed in the instruction `enum`.
This happens due to some LLVM specific edge cases.

Nonetheless, an alias should never be **decoded** as real instruction.

If you find an alias which is decoded as a real instruction, please let us know.
Such an instruction is ill-defined in LLVM and should be fixed upstream.

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