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Merge branch 'next' into auto-sync-aarch64
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@Rot127
Rot127 authored Aug 5, 2023
2 parents f921825 + a4df92e commit fe58530
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Showing 36 changed files with 2,044 additions and 814 deletions.
1 change: 1 addition & 0 deletions .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,7 @@ tests/test_evm
tests/test_wasm
tests/test_mos65xx
tests/test_bpf
tests/test_sh
tests/test_riscv

# regress binaries
Expand Down
121 changes: 99 additions & 22 deletions arch/TriCore/TriCoreDisassembler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -425,6 +425,7 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
unsigned off10_0 = fieldFromInstruction_4(Insn, 16, 6);
unsigned off10_1 = fieldFromInstruction_4(Insn, 28, 4);
unsigned off10 = (off10_0 << 0) | (off10_1 << 6);
bool is_store = false;

unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
Expand All @@ -440,32 +441,83 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
}

if (desc->NumOperands == 2) {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
switch (MCInst_getOpcode(Inst)) {
case TRICORE_ST_A_bo_r:
case TRICORE_ST_A_bo_c:
case TRICORE_ST_B_bo_r:
case TRICORE_ST_B_bo_c:
case TRICORE_ST_D_bo_r:
case TRICORE_ST_D_bo_c:
case TRICORE_ST_DA_bo_r:
case TRICORE_ST_DA_bo_c:
case TRICORE_ST_H_bo_r:
case TRICORE_ST_H_bo_c:
case TRICORE_ST_Q_bo_r:
case TRICORE_ST_Q_bo_c:
case TRICORE_ST_W_bo_r:
case TRICORE_ST_W_bo_c:
case TRICORE_SWAP_W_bo_r:
case TRICORE_SWAP_W_bo_c:
case TRICORE_SWAPMSK_W_bo_c:
case TRICORE_SWAPMSK_W_bo_r: {
is_store = true;
break;
}
}

if (desc->NumOperands == 2) {
if (desc->OpInfo[1].OperandType == MCOI_OPERAND_REGISTER) {
return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
// we have [reg+r] instruction
if (is_store) {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
} else {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
}
} else {
// we have one of the CACHE instructions without destination reg
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;

MCOperand_CreateImm0(Inst, off10);
}
return MCDisassembler_Success;
}

if (desc->NumOperands > 2) {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
if (is_store) {
// we have [reg+c] instruction
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;

status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
} else {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;

status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
MCOperand_CreateImm0(Inst, off10);
}

Expand Down Expand Up @@ -649,8 +701,13 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
MCOperand_CreateImm0(Inst, const16);
} else {
MCOperand_CreateImm0(Inst, const16);
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder);
if (MCInst_getOpcode(Inst) == TRICORE_MTCR_rlc) {
status =
DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
} else {
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder);
}
if (status != MCDisassembler_Success)
return status;
}
Expand Down Expand Up @@ -699,10 +756,24 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
}

if (desc->NumOperands > 1) {
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
switch (MCInst_getOpcode(Inst)) {
case TRICORE_ABSS_rr:
case TRICORE_ABSS_H_rr:
case TRICORE_ABS_H_rr:
case TRICORE_ABS_B_rr:
case TRICORE_ABS_rr: {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
break;
default:
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
Decoder);
}
if (status != MCDisassembler_Success)
return status;
}
}
}

if (desc->NumOperands > 2) {
Expand Down Expand Up @@ -1259,7 +1330,13 @@ static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
return status;

if (desc->NumOperands == 3) {
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
switch (MCInst_getOpcode(Inst)) {
case TRICORE_EXTR_rrrr:
case TRICORE_EXTR_U_rrrr:
return DecodeRegisterClass(Inst, s3, &desc->OpInfo[2], Decoder);
default:
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
}
}

// Decode s2.
Expand Down
16 changes: 16 additions & 0 deletions arch/TriCore/TriCoreInstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -225,6 +225,19 @@ static void off4_fixup(MCInst *MI, uint64_t *off4)
}
}

static void const8_fixup(MCInst *MI, uint64_t *const8)
{
switch (MCInst_getOpcode(MI)) {
case TRICORE_LD_A_sc:
case TRICORE_ST_A_sc:
case TRICORE_ST_W_sc:
case TRICORE_LD_W_sc: {
*const8 *= 4;
break;
}
}
}

static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
Expand All @@ -236,6 +249,9 @@ static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
if (n == 4) {
off4_fixup(MI, &imm);
}
if (n == 8) {
const8_fixup(MI, &imm);
}

printInt64Bang(O, imm);
fill_imm(MI, imm);
Expand Down
5 changes: 3 additions & 2 deletions bindings/const_generator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@

INCL_DIR = '../include/capstone/'

include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'tricore.h' ]
include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h' ]

template = {
'java': {
Expand All @@ -31,7 +31,7 @@
'comment_close': '',
},
'python': {
'header': "from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM\n"
'header': "from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM\n"
"# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n",
'footer': "",
'line_format': '%s = %s\n',
Expand All @@ -53,6 +53,7 @@
'mos65xx.h': 'mos65xx',
'bpf.h': 'bpf',
'riscv.h': 'riscv',
'sh.h': 'sh',
'tricore.h': ['TRICORE', 'TriCore'],
'comment_open': '#',
'comment_close': '',
Expand Down
2 changes: 1 addition & 1 deletion bindings/python/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ PYTHON3 ?= python3
.PHONY: gen_const install install3 install_cython sdist sdist3 bdist bdist3 clean check

gen_const:
cd .. && $(PYTHON2) const_generator.py python
cd .. && $(PYTHON3) const_generator.py python

install:
rm -rf src/
Expand Down
49 changes: 42 additions & 7 deletions bindings/python/capstone/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -35,10 +35,11 @@
'CS_ARCH_TMS320C64X',
'CS_ARCH_M680X',
'CS_ARCH_EVM',
'CS_ARCH_MOS65XX',
'CS_ARCH_WASM',
'CS_ARCH_BPF',
'CS_ARCH_RISCV',
'CS_ARCH_MOS65XX',
'CS_ARCH_SH',
'CS_ARCH_TRICORE',
'CS_ARCH_ALL',

Expand Down Expand Up @@ -90,6 +91,13 @@
'CS_MODE_MOS65XX_65816_LONG_M',
'CS_MODE_MOS65XX_65816_LONG_X',
'CS_MODE_MOS65XX_65816_LONG_MX',
'CS_MODE_SH2',
'CS_MODE_SH2A',
'CS_MODE_SH3',
'CS_MODE_SH4',
'CS_MODE_SH4A',
'CS_MODE_SHFPU',
'CS_MODE_SHDSP',
'CS_MODE_TRICORE_110',
'CS_MODE_TRICORE_120',
'CS_MODE_TRICORE_130',
Expand Down Expand Up @@ -207,7 +215,7 @@
CS_ARCH_WASM = 13
CS_ARCH_BPF = 14
CS_ARCH_RISCV = 15
# CS_ARCH_SH = 16
CS_ARCH_SH = 16
CS_ARCH_TRICORE = 17
CS_ARCH_MAX = 18
CS_ARCH_ALL = 0xFFFF
Expand Down Expand Up @@ -261,6 +269,13 @@
CS_MODE_MOS65XX_65816_LONG_M = (1 << 5) # MOS65XXX WDC 65816, 16-bit m, 8-bit x
CS_MODE_MOS65XX_65816_LONG_X = (1 << 6) # MOS65XXX WDC 65816, 8-bit m, 16-bit x
CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X
CS_MODE_SH2 = 1 << 1 # SH2
CS_MODE_SH2A = 1 << 2 # SH2A
CS_MODE_SH3 = 1 << 3 # SH3
CS_MODE_SH4 = 1 << 4 # SH4
CS_MODE_SH4A = 1 << 5 # SH4A
CS_MODE_SHFPU = 1 << 6 # w/ FPU
CS_MODE_SHDSP = 1 << 7 # w/ DSP
CS_MODE_TRICORE_110 = 1 << 1 # Tricore 1.1
CS_MODE_TRICORE_120 = 1 << 2 # Tricore 1.2
CS_MODE_TRICORE_130 = 1 << 3 # Tricore 1.3
Expand Down Expand Up @@ -425,7 +440,7 @@ def copy_ctypes_list(src):
return [copy_ctypes(n) for n in src]

# Weird import placement because these modules are needed by the below code but need the above functions
from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, tricore
from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore

class _cs_arch(ctypes.Union):
_fields_ = (
Expand All @@ -445,6 +460,7 @@ class _cs_arch(ctypes.Union):
('wasm', wasm.CsWasm),
('bpf', bpf.CsBPF),
('riscv', riscv.CsRISCV),
('sh', sh.CsSH),
('tricore', tricore.CsTriCore),
)

Expand Down Expand Up @@ -725,6 +741,23 @@ def groups(self):
return self._raw.detail.contents.groups[:self._raw.detail.contents.groups_count]

raise CsError(CS_ERR_DETAIL)

# return whether instruction has writeback operands.
@property
def writeback(self):
if self._raw.id == 0:
raise CsError(CS_ERR_SKIPDATA)

if self._cs._diet:
# Diet engine cannot provide @writeback.
raise CsError(CS_ERR_DIET)

if self._cs._detail:
if hasattr(self, 'arm64_writeback'):
return self.arm64_writeback
return self._raw.detail.contents.writeback

raise CsError(CS_ERR_DETAIL)

def __gen_detail(self):
if self._raw.id == 0:
Expand All @@ -733,10 +766,10 @@ def __gen_detail(self):

arch = self._cs.arch
if arch == CS_ARCH_ARM:
(self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, self.cc, self.update_flags, \
self.writeback, self.post_index, self.mem_barrier, self.operands) = arm.get_arch_info(self._raw.detail.contents.arch.arm)
(self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, self.cc, self.vcc, self.update_flags, \
self.post_index, self.mem_barrier, self.pred_mask, self.operands) = arm.get_arch_info(self._raw.detail.contents.arch.arm)
elif arch == CS_ARCH_ARM64:
(self.cc, self.update_flags, self.writeback, self.post_index, self.operands) = \
(self.cc, self.update_flags, self.arm64_writeback, self.post_index, self.operands) = \
arm64.get_arch_info(self._raw.detail.contents.arch.arm64)
elif arch == CS_ARCH_X86:
(self.prefix, self.opcode, self.rex, self.addr_size, \
Expand Down Expand Up @@ -772,6 +805,8 @@ def __gen_detail(self):
(self.operands) = bpf.get_arch_info(self._raw.detail.contents.arch.bpf)
elif arch == CS_ARCH_RISCV:
(self.need_effective_addr, self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.riscv)
elif arch == CS_ARCH_SH:
(self.sh_insn, self.sh_size, self.operands) = sh.get_arch_info(self._raw.detail.contents.arch.sh)
elif arch == CS_ARCH_TRICORE:
(self.update_flags, self.operands) = tricore.get_arch_info(self._raw.detail.contents.arch.tricore)

Expand Down Expand Up @@ -1240,7 +1275,7 @@ def debug():
"sysz": CS_ARCH_SYSZ, 'xcore': CS_ARCH_XCORE, "tms320c64x": CS_ARCH_TMS320C64X,
"m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
'wasm': CS_ARCH_WASM,
'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH,
}

all_archs = ""
Expand Down
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