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Merge branch 'dev'
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merging dev back to master. Updates for tb changes.
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@lsteveol
lsteveol committed Mar 14, 2021
2 parents 75211f3 + c9252cc commit 20432d7
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5 changes: 5 additions & 0 deletions .gitignore
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**/*.log
**/*.lx2


**/CVS/*
59 changes: 39 additions & 20 deletions docs/source/regs.rst
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Expand Up @@ -10,11 +10,12 @@ Description:
.. table::
:widths: 25 10 10 10 50

======= ======== ======== ========== ================================================
Name Index Type Reset Description
======= ======== ======== ========== ================================================
SWRESET [0] RW 0x1 Main reset. Must be cleared prior to operation.
======= ======== ======== ========== ================================================
=========== ======== ======== ========== ================================================
Name Index Type Reset Description
=========== ======== ======== ========== ================================================
SWRESET [0] RW 0x1 Main reset. Must be cleared prior to operation.
SWRESET_MUX [1] RW 0x0 0 - Use logic, 1 - Use register
=========== ======== ======== ========== ================================================


ENABLE
Expand All @@ -27,11 +28,12 @@ Description:
.. table::
:widths: 25 10 10 10 50

====== ======== ======== ========== ======================================================================================================
Name Index Type Reset Description
====== ======== ======== ========== ======================================================================================================
ENABLE [0] RW 0x0 Main enable. Must be set prior to operation. Any configurations should be performed prior to enabling.
====== ======== ======== ========== ======================================================================================================
========== ======== ======== ========== ======================================================================================================
Name Index Type Reset Description
========== ======== ======== ========== ======================================================================================================
ENABLE [0] RW 0x0 Main enable. Must be set prior to operation. Any configurations should be performed prior to enabling.
ENABLE_MUX [1] RW 0x0 0 - Use logic, 1 - Use register
========== ======== ======== ========== ======================================================================================================


INTERRUPT_STATUS
Expand Down Expand Up @@ -137,10 +139,27 @@ Description:
============= ======== ======== ========== =======================================


SHORT_PACKET_MAX
----------------

Address: 0x1c

Description:

.. table::
:widths: 25 10 10 10 50

================ ======== ======== ========== ===================================================================
Name Index Type Reset Description
================ ======== ======== ========== ===================================================================
SHORT_PACKET_MAX [7:0] RW 0x2f This setting allows you to change the window for short/long packets
================ ======== ======== ========== ===================================================================


SW_ATTR_ADDR_DATA
-----------------

Address: 0x1c
Address: 0x20

Description:

Expand All @@ -158,7 +177,7 @@ Description:
SW_ATTR_CONTROLS
----------------

Address: 0x20
Address: 0x24

Description:

Expand All @@ -176,7 +195,7 @@ Description:
SW_ATTR_DATA_READ
-----------------

Address: 0x24
Address: 0x28

Description:

Expand All @@ -193,7 +212,7 @@ Description:
SW_ATTR_FIFO_STATUS
-------------------

Address: 0x28
Address: 0x2c

Description:

Expand All @@ -213,7 +232,7 @@ Description:
SW_ATTR_SHADOW_UPDATE
---------------------

Address: 0x2c
Address: 0x30

Description:

Expand All @@ -230,7 +249,7 @@ Description:
SW_ATTR_EFFECTIVE_UPDATE
------------------------

Address: 0x30
Address: 0x34

Description:

Expand All @@ -247,7 +266,7 @@ Description:
STATE_STATUS
------------

Address: 0x34
Address: 0x38

Description:

Expand All @@ -268,7 +287,7 @@ Description:
DEBUG_BUS_CTRL
--------------

Address: 0x38
Address: 0x3c

Description: Debug observation bus selection for signals that have a mux override

Expand All @@ -278,14 +297,14 @@ Description: Debug observation bus selection for signals that have a mux overrid
================== ======== ======== ========== ================================
Name Index Type Reset Description
================== ======== ======== ========== ================================
DEBUG_BUS_CTRL_SEL [1:0] RW 0x0 Select signal for DEBUG_BUS_CTRL
DEBUG_BUS_CTRL_SEL [2:0] RW 0x0 Select signal for DEBUG_BUS_CTRL
================== ======== ======== ========== ================================


DEBUG_BUS_STATUS
----------------

Address: 0x3c
Address: 0x40

Description: Debug observation bus for signals that have a mux override

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28 changes: 14 additions & 14 deletions docs/source/slink_attributes.rst
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Expand Up @@ -11,18 +11,18 @@ S-Link Attributes
0x2 active_txs 3 0 NUM_TX_LANES_CLOG2 Active TX lanes
0x3 active_rxs 3 0 NUM_RX_LANES_CLOG2 Active RX lanes
0x8 hard_reset_us 10 0 100 Time (in us) at which a Hard Reset Condition is detected.
0x10 px_clk_trail 8 0 32 Number of clock cycles to run the bitclk when going to a P state that doesn't supply the bitclk
0x20 p1_ts1_tx 16 0 32 TS1s to send if exiting from P1
0x21 p1_ts1_rx 16 0 32 TS1s to receive if exiting from P1
0x22 p1_ts2_tx 16 0 4 TS2s to send if exiting from P1
0x23 p1_ts2_rx 16 0 4 TS2s to receive if exiting from P1
0x24 p2_ts1_tx 16 0 64 TS1s to send if exiting from P2
0x25 p2_ts1_rx 16 0 64 TS1s to receive if exiting from P2
0x26 p2_ts2_tx 16 0 8 TS2s to send if exiting from P2
0x27 p2_ts2_rx 16 0 8 TS2s to receive if exiting from P2
0x28 p3r_ts1_tx 16 0 128 TS1s to send if exiting from P3 or when coming out of reset
0x29 p3r_ts1_rx 16 0 128 TS1s to receive if exiting from P3 or when coming out of reset
0x2a p3r_ts2_tx 16 0 16 TS2s to send if exiting from P3 or when coming out of reset
0x2b p3r_ts2_rx 16 0 16 TS2s to receive if exiting from P3 or when coming out of reset
0x30 sync_freq 8 0 15 How often SYNC Ordered Sets are sent during training
0x10 px_clk_trail 8 0 PX_CLK_TRAIL_RESET Number of clock cycles to run the bitclk when going to a P state that doesn't supply the bitclk
0x20 p1_ts1_tx 16 0 P1_TS1_TX_RESET TS1s to send if exiting from P1
0x21 p1_ts1_rx 16 0 P1_TS1_RX_RESET TS1s to receive if exiting from P1
0x22 p1_ts2_tx 16 0 P1_TS2_TX_RESET TS2s to send if exiting from P1
0x23 p1_ts2_rx 16 0 P1_TS2_RX_RESET TS2s to receive if exiting from P1
0x24 p2_ts1_tx 16 0 P2_TS1_TX_RESET TS1s to send if exiting from P2
0x25 p2_ts1_rx 16 0 P2_TS1_RX_RESET TS1s to receive if exiting from P2
0x26 p2_ts2_tx 16 0 P2_TS2_TX_RESET TS2s to send if exiting from P2
0x27 p2_ts2_rx 16 0 P2_TS2_RX_RESET TS2s to receive if exiting from P2
0x28 p3r_ts1_tx 16 0 P3R_TS1_TX_RESET TS1s to send if exiting from P3 or when coming out of reset
0x29 p3r_ts1_rx 16 0 P3R_TS1_RX_RESET TS1s to receive if exiting from P3 or when coming out of reset
0x2a p3r_ts2_tx 16 0 P3R_TS2_TX_RESET TS2s to send if exiting from P3 or when coming out of reset
0x2b p3r_ts2_rx 16 0 P3R_TS2_RX_RESET TS2s to receive if exiting from P3 or when coming out of reset
0x30 sync_freq 8 0 SYNC_FREQ_RESET How often SYNC Ordered Sets are sent during training
======== ============= ====== ======== ================== ===============================================================================================
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