Verilog

This repo will take you through different verilog projects

Name		Name	Last commit message	Last commit date
Latest commit History 160 Commits
16 x 1 Mux		16 x 1 Mux
4-bit ripple carry adder		4-bit ripple carry adder
And Gate		And Gate
BCD to 7-segment		BCD to 7-segment
CMOS NAND		CMOS NAND
CMOS NOT		CMOS NOT
Counter		Counter
ESD		ESD
Full Adder		Full Adder
Half Adder		Half Adder
Half Subtractor		Half Subtractor
Morris		Morris
NOT Gate		NOT Gate
OR Gate		OR Gate
Operators		Operators
Perl		Perl
Pipeline Example 1		Pipeline Example 1
Priority Encoder		Priority Encoder
Register Bank		Register Bank
Summer Practice Problems		Summer Practice Problems
XOR Gate		XOR Gate
README.md		README.md

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