Increase uart test clock speed

This is to potentially better catch erros like described in stm32-rs#260 ealier.
Sh3Rm4n · Jul 28, 2021 · 70d4e02 · 70d4e02
1 parent 6530d6c
commit 70d4e02
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/testsuite/tests/uart.rs b/testsuite/tests/uart.rs
@@ -91,7 +91,11 @@ mod tests {
 
         let mut rcc = dp.RCC.constrain();
         let mut flash = dp.FLASH.constrain();
-        let clocks = rcc.cfgr.freeze(&mut flash.acr);
+        let clocks = rcc
+            .cfgr
+            .use_hse(8.MHz())
+            .sysclk(64.MHz())
+            .freeze(&mut flash.acr);
         let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
         let mut gpiob = dp.GPIOB.split(&mut rcc.ahb);