TCB CCMP ignoring upper 8 bits #372
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I've been looking at porting my "arbitrary" clock divider code across from ATtiny3227 to AVR128DB48 (in preparation for another move with AVR DD but just practising with Dxcore - even though I know it is in megaTinyCore). It fell over quite quickly and working back, I seem to have isolated it to the TCB1 not setting it's CCMP register(s) to anything higher than
Results in a pulse period (ie the time between the rising edge of two sequential pulses, not the width of the pulse when in high logic state) the same as if you write Can anyone please comment, tell me I should be doing something different for the AVR128DB48 from the ATtiny3227 or show me how to "properly" set the 16 bit CCMP registers if I have done it unreliably above? |
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Aha, adding |
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See the errata, cmpl/h is always treated as a 16 bit register as described
in the accessing 16-nitregisters secttion of the datasheet, regardless of
mode
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On Thu, Dec 1, 2022, 21:02 SimonMerrett ***@***.***> wrote:
Aha, adding TCB1.CTRLB = 0; seemed to do the trick. Does the core take
over TCB1 for 8 bit PWM in a way I missed in megaTinyCore?
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Aha, adding
TCB1.CTRLB = 0;
seemed to do the trick. Does the core take over TCB1 for 8 bit PWM in a way I missed in megaTinyCore?