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Enabled test for attributes on parameters.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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67
tests/reference-out/attrib03_parameter/attrib03_parameter.ref.il
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# Generated by Yosys 0.8+498 (git sha1 abef145f, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) | ||
autoidx 3 | ||
attribute \dynports 1 | ||
attribute \cells_not_processed 1 | ||
attribute \src "attrib03_parameter.v:1" | ||
module \bar | ||
|
||
attribute \bus_width 1 | ||
parameter \WIDTH | ||
attribute \src "attrib03_parameter.v:14" | ||
wire width 2 $0\out[1:0] | ||
attribute \src "attrib03_parameter.v:16" | ||
wire width 32 $add$attrib03_parameter.v:16$2_Y | ||
attribute \src "attrib03_parameter.v:9" | ||
wire input 1 \clk | ||
attribute \src "attrib03_parameter.v:11" | ||
wire width 2 input 3 \inp | ||
attribute \src "attrib03_parameter.v:12" | ||
wire width 2 output 4 \out | ||
attribute \src "attrib03_parameter.v:10" | ||
wire input 2 \rst | ||
attribute \src "attrib03_parameter.v:16" | ||
cell $add $add$attrib03_parameter.v:16$2 | ||
parameter \A_SIGNED 0 | ||
parameter \A_WIDTH 2 | ||
parameter \B_SIGNED 0 | ||
parameter \B_WIDTH 32 | ||
parameter \Y_WIDTH 32 | ||
connect \A \inp | ||
connect \B 5 | ||
connect \Y $add$attrib03_parameter.v:16$2_Y | ||
end | ||
attribute \src "attrib03_parameter.v:14" | ||
process $proc$attrib03_parameter.v:14$1 | ||
assign $0\out[1:0] \out | ||
attribute \src "attrib03_parameter.v:15" | ||
switch \rst | ||
case 1'1 | ||
assign $0\out[1:0] 2'00 | ||
case | ||
assign $0\out[1:0] $add$attrib03_parameter.v:16$2_Y [1:0] | ||
end | ||
sync posedge \clk | ||
update \out $0\out[1:0] | ||
end | ||
end | ||
attribute \cells_not_processed 1 | ||
attribute \src "attrib03_parameter.v:20" | ||
module \foo | ||
attribute \src "attrib03_parameter.v:21" | ||
wire input 1 \clk | ||
attribute \src "attrib03_parameter.v:23" | ||
wire width 8 input 3 \inp | ||
attribute \src "attrib03_parameter.v:24" | ||
wire width 8 output 4 \out | ||
attribute \src "attrib03_parameter.v:22" | ||
wire input 2 \rst | ||
attribute \module_not_derived 1 | ||
attribute \src "attrib03_parameter.v:26" | ||
cell \bar \bar_instance | ||
parameter signed \WIDTH 8 | ||
connect $1 \clk | ||
connect $2 \rst | ||
connect $3 \inp | ||
connect $4 \out | ||
end | ||
end |
217 changes: 217 additions & 0 deletions
217
tests/reference-out/attrib03_parameter/attrib03_parameter.ref.json
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{ | ||
"creator": "Yosys 0.8+498 (git sha1 abef145f, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)", | ||
"modules": { | ||
"bar": { | ||
"attributes": { | ||
"dynports": 1, | ||
"cells_not_processed": 1, | ||
"src": "attrib03_parameter.v:1" | ||
}, | ||
"parameters": { | ||
"WIDTH": { | ||
"attributes": { | ||
"bus_width": 1 | ||
}, | ||
"default": 2 | ||
} | ||
}, | ||
"ports": { | ||
"clk": { | ||
"direction": "input", | ||
"bits": [ 2 ] | ||
}, | ||
"rst": { | ||
"direction": "input", | ||
"bits": [ 3 ] | ||
}, | ||
"inp": { | ||
"direction": "input", | ||
"bits": [ 4, 5 ] | ||
}, | ||
"out": { | ||
"direction": "output", | ||
"bits": [ 6, 7 ] | ||
} | ||
}, | ||
"cells": { | ||
"$add$attrib03_parameter.v:16$2": { | ||
"hide_name": 1, | ||
"type": "$add", | ||
"parameters": { | ||
"A_SIGNED": 0, | ||
"A_WIDTH": 2, | ||
"B_SIGNED": 0, | ||
"B_WIDTH": 32, | ||
"Y_WIDTH": 32 | ||
}, | ||
"attributes": { | ||
"src": "attrib03_parameter.v:16" | ||
}, | ||
"port_directions": { | ||
"A": "input", | ||
"B": "input", | ||
"Y": "output" | ||
}, | ||
"connections": { | ||
"A": { | ||
"bits": [ 4, 5 ], | ||
"attributes": { | ||
} | ||
}, | ||
"B": { | ||
"bits": [ "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], | ||
"attributes": { | ||
} | ||
}, | ||
"Y": { | ||
"bits": [ 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 ], | ||
"attributes": { | ||
} | ||
} | ||
} | ||
} | ||
}, | ||
"netnames": { | ||
"$0\\out[1:0]": { | ||
"hide_name": 1, | ||
"bits": [ 40, 41 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:14" | ||
} | ||
}, | ||
"$add$attrib03_parameter.v:16$2_Y": { | ||
"hide_name": 1, | ||
"bits": [ 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:16" | ||
} | ||
}, | ||
"clk": { | ||
"hide_name": 0, | ||
"bits": [ 2 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:9" | ||
} | ||
}, | ||
"inp": { | ||
"hide_name": 0, | ||
"bits": [ 4, 5 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:11" | ||
} | ||
}, | ||
"out": { | ||
"hide_name": 0, | ||
"bits": [ 6, 7 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:12" | ||
} | ||
}, | ||
"rst": { | ||
"hide_name": 0, | ||
"bits": [ 3 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:10" | ||
} | ||
} | ||
} | ||
}, | ||
"foo": { | ||
"attributes": { | ||
"cells_not_processed": 1, | ||
"src": "attrib03_parameter.v:20" | ||
}, | ||
"parameters": { | ||
}, | ||
"ports": { | ||
"clk": { | ||
"direction": "input", | ||
"bits": [ 2 ] | ||
}, | ||
"rst": { | ||
"direction": "input", | ||
"bits": [ 3 ] | ||
}, | ||
"inp": { | ||
"direction": "input", | ||
"bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ] | ||
}, | ||
"out": { | ||
"direction": "output", | ||
"bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ] | ||
} | ||
}, | ||
"cells": { | ||
"bar_instance": { | ||
"hide_name": 0, | ||
"type": "bar", | ||
"parameters": { | ||
"WIDTH": 8 | ||
}, | ||
"attributes": { | ||
"module_not_derived": 1, | ||
"src": "attrib03_parameter.v:26" | ||
}, | ||
"port_directions": { | ||
"$1": "output", | ||
"$2": "output", | ||
"$3": "output", | ||
"$4": "output" | ||
}, | ||
"connections": { | ||
"$1": { | ||
"bits": [ 2 ], | ||
"attributes": { | ||
} | ||
}, | ||
"$2": { | ||
"bits": [ 3 ], | ||
"attributes": { | ||
} | ||
}, | ||
"$3": { | ||
"bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ], | ||
"attributes": { | ||
} | ||
}, | ||
"$4": { | ||
"bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ], | ||
"attributes": { | ||
} | ||
} | ||
} | ||
} | ||
}, | ||
"netnames": { | ||
"clk": { | ||
"hide_name": 0, | ||
"bits": [ 2 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:21" | ||
} | ||
}, | ||
"inp": { | ||
"hide_name": 0, | ||
"bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:23" | ||
} | ||
}, | ||
"out": { | ||
"hide_name": 0, | ||
"bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:24" | ||
} | ||
}, | ||
"rst": { | ||
"hide_name": 0, | ||
"bits": [ 3 ], | ||
"attributes": { | ||
"src": "attrib03_parameter.v:22" | ||
} | ||
} | ||
} | ||
} | ||
} | ||
} |
58 changes: 58 additions & 0 deletions
58
tests/reference-out/attrib03_parameter/attrib03_parameter.ref.v
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/* Generated by Yosys 0.8+498 (git sha1 abef145f, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) */ | ||
|
||
(* dynports = 1 *) | ||
(* cells_not_processed = 1 *) | ||
(* src = "attrib03_parameter.v:1" *) | ||
module bar(clk, rst, inp, out); | ||
(* bus_width = 32'd1 *) | ||
parameter \WIDTH = 32'd2; | ||
(* src = "attrib03_parameter.v:14" *) | ||
reg [1:0] _0_; | ||
(* src = "attrib03_parameter.v:16" *) | ||
wire [31:0] _1_; | ||
(* src = "attrib03_parameter.v:9" *) | ||
input clk; | ||
(* src = "attrib03_parameter.v:11" *) | ||
input [1:0] inp; | ||
(* src = "attrib03_parameter.v:12" *) | ||
output [1:0] out; | ||
reg [1:0] out; | ||
(* src = "attrib03_parameter.v:10" *) | ||
input rst; | ||
assign _1_ = inp + (* src = "attrib03_parameter.v:16" *) 32'd5; | ||
always @* begin | ||
_0_ = out; | ||
casez (rst) | ||
1'h1: | ||
_0_ = 2'h0; | ||
default: | ||
_0_ = _1_[1:0]; | ||
endcase | ||
end | ||
always @(posedge clk) begin | ||
out <= _0_; | ||
end | ||
endmodule | ||
|
||
(* cells_not_processed = 1 *) | ||
(* src = "attrib03_parameter.v:20" *) | ||
module foo(clk, rst, inp, out); | ||
(* src = "attrib03_parameter.v:21" *) | ||
input clk; | ||
(* src = "attrib03_parameter.v:23" *) | ||
input [7:0] inp; | ||
(* src = "attrib03_parameter.v:24" *) | ||
output [7:0] out; | ||
(* src = "attrib03_parameter.v:22" *) | ||
input rst; | ||
(* module_not_derived = 32'd1 *) | ||
(* src = "attrib03_parameter.v:26" *) | ||
bar #( | ||
.WIDTH(32'sd8) | ||
) bar_instance ( | ||
clk, | ||
rst, | ||
inp, | ||
out | ||
); | ||
endmodule |