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Merge pull request #29 from litghost/fix_carry_techmap
Dedicated top of carry pin is sourced from O[Y_WIDTH].
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#!/bin/bash | ||
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set -ex | ||
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# Test base testbench | ||
iverilog -DVCDFILE=\"test_arith_no_synth.vcd\" -T typ -o test_arith_no_synth \ | ||
test_arith_tb.v test_arith.v | ||
vvp -N test_arith_no_synth | ||
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# Test Xilinx flow | ||
../../../yosys -v2 -l test_arith_xilinx.log -p synth_xilinx \ | ||
-o test_arith_xilinx.v \ | ||
test_arith.v | ||
iverilog -DVCDFILE=\"test_arith_xilinx.vcd\" -T typ -o test_arith_xilinx \ | ||
test_arith_tb.v test_arith_xilinx.v \ | ||
../cells_sim.v | ||
vvp -N test_arith_xilinx | ||
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# Test Xilinx (VPR) flow | ||
../../../yosys -v2 -l test_arith_xilinx_vpr.log -p "synth_xilinx -vpr" \ | ||
-o test_arith_xilinx_vpr.v \ | ||
test_arith.v | ||
iverilog \ | ||
-D_EXPLICIT_CARRY \ | ||
-DVCDFILE=\"test_arith_xilinx_vpr.vcd\" -T typ \ | ||
-o test_arith_xilinx_vpr \ | ||
test_arith_tb.v test_arith_xilinx_vpr.v \ | ||
../cells_sim.v | ||
vvp -N test_arith_xilinx_vpr |
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module test_arith( | ||
input [7:0] a, | ||
input [7:0] b, | ||
output [7:0] add, | ||
output [0:0] add_cout, | ||
output [7:0] minus, | ||
output [0:0] minus_cout, | ||
output threshold | ||
); | ||
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parameter INCREMENT = 8; | ||
parameter THRESHOLD = 16; | ||
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assign {add_cout, add} = a + b; | ||
assign {minus_cout, minus} = a - b; | ||
assign threshold = (a + INCREMENT) >= THRESHOLD; | ||
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endmodule |
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`timescale 1ns/1ps | ||
`default_nettype none | ||
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`ifndef VCDFILE | ||
`define VCDFILE "test_arith_tb.vcd" | ||
`endif | ||
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module test; | ||
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task tbassert(input a, input reg [512:0] s); | ||
begin | ||
if (a==0) begin | ||
$display("**********************************************************"); | ||
$display("* ASSERT FAILURE (@%d): %-s", $time, s); | ||
$display("**********************************************************"); | ||
$dumpflush; | ||
$finish_and_return(-1); | ||
end | ||
end | ||
endtask | ||
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reg [7:0] a = 0; | ||
reg [7:0] b = 0; | ||
wire [7:0] add; | ||
wire add_cout; | ||
wire [7:0] minus; | ||
wire minus_cout; | ||
wire threshold; | ||
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test_arith #( | ||
.INCREMENT(8), | ||
.THRESHOLD(16) | ||
) unt ( | ||
.a(a), | ||
.b(b), | ||
.add(add), | ||
.add_cout(add_cout), | ||
.minus(minus), | ||
.minus_cout(minus_cout), | ||
.threshold(threshold) | ||
); | ||
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initial begin | ||
$dumpfile(`VCDFILE); | ||
$dumpvars; | ||
#0.9 | ||
a = 8'b0000_0000; | ||
b = 8'b0000_0000; | ||
#0.1 | ||
tbassert(add == 8'b0000_0000, "zero add"); | ||
tbassert(add_cout == 1'b0, "zero add carry"); | ||
tbassert(minus == 8'b0000_0000, "zero subtract"); | ||
tbassert(minus_cout == 1'b0, "zero subtract carry"); | ||
tbassert(threshold == 1'b0, "threshold not met"); | ||
#0.9 // 2 | ||
a = 8'b0000_0001; | ||
b = 8'b0000_0001; | ||
#0.1 | ||
tbassert(add == 8'b0000_0010, "simple add"); | ||
tbassert(add_cout == 1'b0, "simple add carry"); | ||
tbassert(minus == 8'b0000_0000, "simple subtract"); | ||
tbassert(minus_cout == 1'b0, "simple subtract carry"); | ||
#0.9 // 3 | ||
a = 8'b1111_1111; | ||
b = 8'b0000_0001; | ||
#0.1 | ||
tbassert(add == 8'b0000_0000, "overflow add"); | ||
tbassert(add_cout == 1'b1, "overflow add carry"); | ||
tbassert(minus == 8'b1111_1110, "simple subtract carry 2"); | ||
tbassert(minus_cout == 1'b0, "simple subtract carry 2"); | ||
#0.9 // 4 | ||
a = 8'b0000_0001; | ||
b = 8'b1111_1111; | ||
#0.1 | ||
tbassert(add == 8'b0000_0000, "overflow add 2"); | ||
tbassert(add_cout == 1'b1, "overflow add 2 carry"); | ||
tbassert(minus == 8'b0000_0010, "underflow subtract"); | ||
tbassert(minus_cout == 1'b1, "underflow subtract carry"); | ||
#0.9 // 5 | ||
a = 8'd8; | ||
#0.1 | ||
tbassert(threshold, "threshold met"); | ||
#0.9 // 6 | ||
a = 8'd7; | ||
#0.1 | ||
tbassert(!threshold, "threshold not met"); | ||
#1 $finish; | ||
end | ||
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endmodule |