Sync master+wip with upstream #21
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Signed-off-by: David Shah <dave@ds0.me>
memory_bram: Reset make_transp when growing read ports
Libertyfixes: accept superfluous ; at end of group.
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Build Verilog parser with -DYYMAXDEPTH=100000
RFC: Add a pmux-to-shiftx optimisation to proc_mux
Signed-off-by: David Shah <dave@ds0.me>
Refine memory support to deal with general Verilog memory definitions.
memory_bram: Consider read enable for address expansion register
last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: David Shah <dave@ds0.me>
memory_bram: Fix multiport make_transp
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Recognise default entry in case even if all cases covered (fix for #931)
Fixing issues in CycloneV cell sim
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Add additional cells sim models for core 7-series primitives.
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