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Support for attributes on parameters in Verilog #25
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…their default values. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…ctionality. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Do you need to update the chparam
and setparam
+ equivalent commands to use the new iterators for parameter lists?
@mithro I didn't do anything to |
…rmer functionality." This reverts commit fece472. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…the Verilog backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Now the
The functionality regarding The dict I also updated the JSON, ilang and Verilog backends. Attributes of parameters are now visible when using the |
…alues though. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…heir names violate Verilog syntax. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Looking good. Two general thoughts:
- Are there tests we should be adding?
- Can we flag out the "cost" of these changes?
backends/verilog/verilog_backend.cc
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{ | ||
for (auto& param : module->avail_parameters) { | ||
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// Skip the parameter if its name begins with '$'. Such names are illegal |
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I don't believe this is correct? You can use escape identifiers to write them out?
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Fixed.
@litghost I already added some tests regarding parsing of parameter attributes and they are merged upstream. I suppose I should add additional tests which will include eg. reading Verilog, writing JSON/ILANG and comparing output with a reference. I haven't found any similar tests in the Yosys tests folder. What do you think ? Regarding the "cost": I believe that the cost can only be observable when processing verilogs with huge number of attributes on parameters. I would need to think of some kind of memory usage and performance tests. I haven't found such tests either. |
…backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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LGTM
@litghost Do not merge. I recently discovered that floating point constants are handled differently than strings and integers. Also a floating point constant is a different object in the AST tree. I added a quick workaround which treats floating point constants as integer 0 but it is not an acceptable solution. In order to fix that I would need either to refactor the Anyway, there is still some work to do with this PR. |
Maybe we should not modify Yosys and simply extract the FASM_PARAM annotation using a coarse parser. I'm not a fan of keeping a Yosys fork forever, and the more that has to change, the less likely they will accept it. @mithro, thoughts? |
…erilog frontend/backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…e JSON backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Anyway I managed to do the fix. So the default value of a parameter can now be floating point. It is correctly loaded by the Verilog frontend and correctly outputted by the Verilog and the JSON backend. The ilang frontend never parsed default values of parameters so I left its functionality intact. |
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LGTM.
@litghost Let's land this and then we can figure out an alternative approach. |
The attribute is specified as a prefix to a declaration, a module item, a statement or a port connection. Three examples are:
The attribute is specified as a suffix to an operator or the function name in a function call.
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@mkurc-ant So, it appears you missed being able to add an attribute to a port connection. See the third item above. Could you fix that? |
I've discussed this issue with Yosys upstream and we agree this is a good idea, however, the way we'd suggest implementing it would be to transform the parameter into a new wire (permanently) driven by the parameter value. That way, it appears post-elaboration, and in the backend too, so that it can be inspected during simulation or used during formal verification too. Would you consider trying this approach instead? |
This PR adds support for attributes on parameters for Verilog.
The Verilog frontend was augmented with parsing and storing attributes of parameters in their AST nodes. Parameter attributes are only stored for those that actually have them. The default value of a parameter is also preserved.