Moved techmaps from Yosys to SymbiFlow #8
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…f the "synth_xilinx" macro. Updated manual accordingly. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…inx" flow accordingly. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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| `ifndef _EXPLICIT_DRAM | ||
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| module RAM64X1D ( |
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What trick are you referring to ? RAM64X1D is recognized by Vivado. And it can be also mapped later to explicit instantation of DPRAM and SPRAM. But this map was moved to SymbiFlow.
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I believe RAM64X1D_1 is a valid Vivado primative that is "DRAM64X1D with clock inversion". Can Yosys emit a DRAM with invert clock? If so, it should map to RAM64X1D_1.
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Might be worth looking at this spreadsheet.
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Seems that I don't have permissions to that document... Anyway, I'll check if Vivado accepts DRAMS with _1.
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I converted the spreadsheet to a markdown document here -> f4pga/f4pga-arch-defs#403
I've added techmaps that allow to synthesize for Vivado P&R using Yosys. I've also moved what was possible of VPR related techmaps according to: f4pga/f4pga-arch-defs#294
The macro code for
synth_xilinxwas modified to accomodate changes. I've also added additional flags that allow to disable DRAM and/or BRAM inference.