Address line width off-by-one

[leolitenstorrent]

Hello PeakRDL Development Team,

It seems that for an address map with size 128 bytes, the Verilog module generated by PeakRDL will have an address line that is 8 bits wide. However, in reality, only 7 bits are required for the address line because the address range only goes from 0 to 127.

I checked your source code and saw the line self.addr_width = self.top_node.size.bit_length() under class DesignState and request that it be changed to self.addr_width = (self.top_node.size - 1).bit_length().

Thank you!

[amykyta3]

I agree this is a bug I must have missed. Thanks for reporting!

I have fixed it and it will be published in the next release