Vivado Synthesis Compatability

[roowatt]

Using latest peakrdl-regblock v0.18.0

I have an issue with synthesis compatability with Vivado 2023.1 when using asynchronous resets (I haven't checked other kinds).

If I have afield without a reset value (ie No reset) then the Vivado synthesiser chokes with a fatal error.

A simplified rdl def is as follows...

addrmap test_case {
name = "Xilinx Vivado Test Case";

    default sw = rw;
    default hw = r;	

    default regwidth = 32;
    default accesswidth = 32;

    addressing = regalign;

	regfile  {
	    default sw = rw;
	    default hw = r;	

		reg {
			field {} field0[16] = 0;
			field {} field1[16] ;
		} reg0;
	} regfile0;
};

Error below...

ERROR: [Synth 8-91] ambiguous clock in event control [/xxxx/peakrdl/build/test_case.sv:294]
ERROR: [Synth 8-6156] failed synthesizing module 'test_case' [/xxxx/peakrdl/build/test_case.sv:4]

[roowatt]

Removed extraneous log file details.

[amykyta3]

Thanks!
I have confirmed the issue and the fix will be in the next release.

[amykyta3]

Published in 0.19.0