Default Value of a Read-Only Field is Generated as a Constant

[kdstrike]

Defining a field as read-only and assigning it a default value in System RDL leads to the generated System Verilog files assigning the default value to the readback signal as a constant. This produces an error in Questa when the field width is larger than the access width because bit splicing is necessary but cannot be done on constant values.

Example System RDL file myFile.rdl

addrmap myAddrMap {
    default accesswidth = 32;

    reg
    {
        name = "64 Bit Register";
        desc = "Example of a 64-bit register used with a 32-bit access bus.";
        regwidth = 64;

        field
        {
            name = "64 Bit Field";
            sw=r; hw=r;
        } myField[64] = 64'hDEADBEEFDEADBEEF;
    } myRegister;
};

Executing peakrdl regblock -o ./ myFile.rdl generates myAddrMap_pkg.sv and myAddrMap.sv. The last two lines in the following section from myAddrMap.sv are what cause the error. That is, the constant deadbeef being spliced to access bits [31:0] and [63:32] separately.

//--------------------------------------------------------------------------
// Readback
//--------------------------------------------------------------------------

logic readback_err;
logic readback_done;
logic [31:0] readback_data;
    
// Assign readback values to a flattened array
logic [31:0] readback_array[2];
assign readback_array[0][31:0] = (decoded_reg_strb.myRegister[0] && !decoded_req_is_wr) ? 64'hdeadbeefdeadbeef[31:0] : '0;
assign readback_array[1][31:0] = (decoded_reg_strb.myRegister[1] && !decoded_req_is_wr) ? 64'hdeadbeefdeadbeef[63:32] : '0;

The error Questa shows as follows and relates to the lines described above.

myAddrMap.sv(139): near "[": syntax error, unexpected '['.
myAddrMap.sv(140): near "[": syntax error, unexpected '['.

[amykyta3]

Thanks for finding and reporting this edge case!

Implemented a fix which will be in the next release.