arm/convolution_3x3_pack1to8_fp16s: prefer ldr/str over ld1/st1 #5603
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Depending on the arch, ldr/str can be faster than ld1/st1, especially
for loading to one lane form. For example, on Cortex A75,
1. execution latency of 'ldr q0' and 'ldr h0' are 5
2. execution latency of 'ld1 {v0.16b}' is 6
3. execution latency of 'ld1 {v0.h}[0]' is 8
On Cortex X3,
1. execution latency of 'ldr q0' and 'ldr h0' are 6
2. execution latency of 'ld1 {v0.16b}' is 6
3. execution latency of 'ld1 {v0.h}[0]' is 8
Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## master #5603 +/- ##
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- Coverage 94.73% 94.58% -0.16%
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Files 786 786
Lines 248543 248542 -1
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- Hits 235462 235084 -378
- Misses 13081 13458 +377 ☔ View full report in Codecov by Sentry. |
nihui
reviewed
Jul 29, 2024
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Thanks for your contribution ! |
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Depending on the arch, ldr/str can be faster than ld1/st1, especially for loading to one lane form. For example
On Cortex A75,
On Cortex X3,