mock-array: add missing signals in .vcd file

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
The-OpenROAD-Project · Jan 13, 2025 · f6f6092 · f6f6092
1 parent 0ff3a4b
commit f6f6092
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/flow/designs/asap7/mock-array/simulate.sh b/flow/designs/asap7/mock-array/simulate.sh
@@ -27,6 +27,7 @@ verilator -Wall --cc \
   --Mdir $OBJ_DIR \
   --top-module MockArray \
   --trace \
+  --trace-underscore \
   $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v \
   $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v \
   $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v \