Merge pull request #2552 from The-OpenROAD-Project-staging/secure-flo…

…w-new_ungrouping New ungrouping logic
The-OpenROAD-Project · Jan 10, 2025 · faaca5d · faaca5d
2 parents d29133c + 913f2dd
commit faaca5d
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Showing 22 changed files with 1,924 additions and 1,854 deletions.
diff --git a/flow/Makefile b/flow/Makefile
@@ -178,9 +178,6 @@ include $(PLATFORM_DIR)/config.mk
 # is no way to escape space in defaults.py and get "foreach" to work.
 $(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
 
-# Enables hierarchical yosys
-export SYNTH_STATS = $(RESULTS_DIR)/synth_stats.txt
-export SYNTH_STATS_SCRIPT = $(SCRIPTS_DIR)/synth_stats.tcl
 # If the design, nor $(PLATFORM_DIR)/config.mk provided a default, provide one here
 export MAX_UNGROUP_SIZE ?= 0
 
@@ -454,13 +451,6 @@ memory:
 
 export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl
 export SYNTH_MEMORY_MAX_BITS ?= 4096
-
-.PHONY: do-yosys-stats
-do-yosys-stats:
-	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
-	(export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \
-	$(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_STATS_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_stats.log)
-
 export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt
 
 $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
@@ -487,7 +477,7 @@ $(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES)
 	$(UNSET_AND_MAKE) do-yosys-canonicalize
 
 $(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil
-	$(UNSET_AND_MAKE) do-yosys-stats do-yosys
+	$(UNSET_AND_MAKE) do-yosys
 
 .PHONY: do-synth
 do-synth:

diff --git a/flow/designs/asap7/aes-block/metadata-base-ok.json b/flow/designs/asap7/aes-block/metadata-base-ok.json
diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json
@@ -1,6 +1,6 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 2310.54,
+        "value": 2293.17,
         "compare": "<="
     },
     "constraints__clocks__count": {
@@ -12,27 +12,27 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 12203,
+        "value": 11853,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 1061,
+        "value": 1031,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 1061,
+        "value": 1031,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 98764,
+        "value": 88188,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -164.76,
+        "value": -198.03,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 7462,
+        "value": 7443,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 531,
+        "value": 515,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {

diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk
@@ -9,7 +9,7 @@ export RTLMP_MAX_INST = 3500
 export RTLMP_MIN_MACRO = 1
 export RTLMP_MAX_MACRO = 5
 
-export MAX_UNGROUP_SIZE ?= 1000
+export MAX_UNGROUP_SIZE ?= 10000
 
 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/riscv32i/*.v))
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/riscv32i/constraint.sdc