asap7: dff.v was missing internal signals

[oharboe]

This caused .vcd files in mock-array not to have pin values for all pins.

[oharboe]

@maliberty Shooting from the hip here. I don't find IQNN, nor IQN exactly in the original behavioral Verilog(which Verilator can't support), but they do exist in the .lib file:

OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_SEQ_RVT_TT_220101.v

Line 44 in 0ff3a4b

wire int_fwire_d, int_fwire_IQN, int_fwire_r;

  cell (DFFASRHQNx1_ASAP7_75t_R) {
    [deleted]
    pin (QN) {
      direction : output;
      function : "IQN";
      power_down_function : "(!VDD) + (VSS)";
      related_ground_pin : VSS;
    [deleted]
    ff (IQN,IQNN) {
      clear : "!SETN";
      clear_preset_var1 : L;
      clear_preset_var2 : L;
      clocked_on : "CLK";
      next_state : "!D";
      power_down_function : "(!VDD) + (VSS)";
      preset : "!RESETN";
    }
  }

[maliberty]

I disagree with this change. There is no need for these in Verilog. The state nodes are internal to Liberty. Perhaps you can expand on what the problem you are trying to solve is.

[oharboe]

I disagree with this change. There is no need for these in Verilog. The state nodes are internal to Liberty. Perhaps you can expand on what the problem you are trying to solve is.

I'm finding pins that are not annotated with activities by the .vcd file

[maliberty]

We seem to be having this conversation in two PRs. Let's close this and discuss in the other.