Skip to content
View TheMightyDuckOfDoom's full-sized avatar

Highlights

  • Pro

Block or report TheMightyDuckOfDoom

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. liberty74 liberty74 Public

    A Fully Open-Source Verilog-to-PCB Flow

    Python 17 4

  2. servisia servisia Public

    Minimal SoC containing a Serv-RV32I Core designed for usage with Liberty74

    Verilog 2

  3. pulp-platform/iDMA pulp-platform/iDMA Public

    A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

    SystemVerilog 98 29

  4. nextpnr nextpnr Public

    Forked from YosysHQ/nextpnr

    nextpnr portable FPGA place and route tool

    C++

  5. projectXCxk projectXCxk Public

    Reverse-engineering of early Xilinx FPGAs

    Python