Change help text to display correct addresses

[phummel]

While the Data Lab Sim module auto adjusts with MMIO address range, the help text address values are not updated accordingly. This fixes the help text to show the updated address values.

[TheThirdOne]

What auto adjustment are you referring to? As the values you are printing are static and final, they shouldn't be able to change during program execution.

Can you give me a scenario where the PR actually changes what the displayed help content is?

[phummel]

The text in the help for Digital Lab Sim has hard coded values for memory addresses. These are correct if the Default memory configuration is used. If I switch to either of the compact memory configurations, the addresses the Digital Lab Sim tool is connected to change to match accordingly. However, the text in the help will still say 0xFFFF0010 instead of 0x00007F10. This change matches the text from the Keyboard and Display Simulator tool that updates with the memory configuration changes.

[TheThirdOne]

Ah, I missed thinking about restarting and relying on the setting being saved from the last launch.

I have merged your contribution in and made DigitalLabSim also update according to the memory configuration on launch of the tool. Thanks for the contribution.

Has Cal Poly been using the compact memory configuration? I have been thinking about making changes to the way memory configurations work so if I would like to know how yall are using it so I can make sure an update wouldn't break anything.

[phummel]

We have just refreshed a course switching to the RISC-V, and so we are working out what tools to use. In the course we implement our own single-cycle RISC-V (RV32i) on an FPGA. I have been using RARS exclusively, so I appreciate the work you have put into this. The memory configuration does not match the hardware we implement in the course, so I created a separate build for my classes with updated addresses. The compact configuration is close, but it was easier for students if everything matched exactly.

[TheThirdOne]

In case you are unaware, Ripes just released a new version that can simulate a single-cycle or 5 stage processor. Given the RARS, only simulates at the instruction level, I would think Ripes would fill in an important role in teaching the implementation of a RISC-V CPU.