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use delay 1T signal to generate tvalid to remote side
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tonyho authored and tonyho committed May 7, 2024
1 parent 1f27726 commit 2eef856
Showing 1 changed file with 60 additions and 53 deletions.
113 changes: 60 additions & 53 deletions vivado/vvd_srcs/caravel_soc/rtl/user/io_serdes/rtl/io_serdes.v
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@

`define USE_FOR_LOOP_Serial_Data_Out_tdata 1

(* DONT_TOUCH = "yes" *) module IO_SERDES #(
module IO_SERDES #(
parameter pUSER_PROJECT_SIDEBAND_WIDTH = 5,
parameter pSERIALIO_WIDTH = 13,
parameter pADDR_WIDTH = 15,
Expand Down Expand Up @@ -78,14 +78,15 @@
input wire [pDATA_WIDTH-1:0] as_is_tdata,
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
input wire [pUSER_PROJECT_SIDEBAND_WIDTH-1:0] as_is_tupsb,
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT
input wire [(pDATA_WIDTH/8)-1:0] as_is_tstrb,
input wire [(pDATA_WIDTH/8)-1:0] as_is_tkeep,
input wire as_is_tlast,
input wire [1:0] as_is_tid,
input wire as_is_tvalid,
input wire [1:0] as_is_tuser,
input wire as_is_tready, //when local side axis switch Rxfifo size <= threshold then as_is_tready=0, this flow control mechanism is for notify remote side do not provide data with is_as_tvalid=1
output wire rxen_out, //output rxen for post synthsis simultation

output wire serial_tclk,
output wire [pSERIALIO_WIDTH-1: 0] serial_txd,
Expand All @@ -97,7 +98,7 @@
output wire [pDATA_WIDTH-1:0] is_as_tdata,
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
output wire [pUSER_PROJECT_SIDEBAND_WIDTH-1:0] is_as_tupsb,
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT
output wire [(pDATA_WIDTH/8)-1:0] is_as_tstrb,
output wire [(pDATA_WIDTH/8)-1:0] is_as_tkeep,
output wire is_as_tlast,
Expand Down Expand Up @@ -125,36 +126,36 @@
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
wire Serial_Data_Out_tupsb_4_1;
wire Serial_Data_Out_tupsb_tlast_tvalid_tready;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
wire Serial_Data_Out_tlast_tvalid_tready;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT
wire Serial_Data_Out_tid_tuser;
wire Serial_Data_Out_tkeep;
wire Serial_Data_Out_tstrb;
wire [pSERIALIO_TDATA_WIDTH-1:0] Serial_Data_Out_tdata;

`ifdef USER_PROJECT_SIDEBAND_SUPPORT
assign serial_txd[pSERIALIO_WIDTH-1:0] = {Serial_Data_Out_tupsb_4_1, Serial_Data_Out_tupsb_tlast_tvalid_tready, Serial_Data_Out_tid_tuser, Serial_Data_Out_tkeep, Serial_Data_Out_tstrb, Serial_Data_Out_tdata[pSERIALIO_TDATA_WIDTH-1:0]};
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
assign serial_txd[pSERIALIO_WIDTH-1:0] = {Serial_Data_Out_tlast_tvalid_tready, Serial_Data_Out_tid_tuser, Serial_Data_Out_tkeep, Serial_Data_Out_tstrb, Serial_Data_Out_tdata[pSERIALIO_TDATA_WIDTH-1:0]};
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT

`ifdef USER_PROJECT_SIDEBAND_SUPPORT
wire Serial_Data_In_tupsb_4_1;
wire Serial_Data_In_tupsb_tlast_tvalid_tready;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
wire Serial_Data_In_tlast_tvalid_tready;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT
wire Serial_Data_In_tid_tuser;
wire Serial_Data_In_tkeep;
wire Serial_Data_In_tstrb;
wire [pSERIALIO_TDATA_WIDTH-1:0] Serial_Data_In_tdata;

`ifdef USER_PROJECT_SIDEBAND_SUPPORT
assign {Serial_Data_In_tupsb_4_1, Serial_Data_In_tupsb_tlast_tvalid_tready, Serial_Data_In_tid_tuser, Serial_Data_In_tkeep, Serial_Data_In_tstrb, Serial_Data_In_tdata[pSERIALIO_TDATA_WIDTH-1:0] } = serial_rxd[pSERIALIO_WIDTH-1:0];
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
assign {Serial_Data_In_tlast_tvalid_tready, Serial_Data_In_tid_tuser, Serial_Data_In_tkeep, Serial_Data_In_tstrb, Serial_Data_In_tdata[pSERIALIO_TDATA_WIDTH-1:0] } = serial_rxd[pSERIALIO_WIDTH-1:0];
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT


reg txen;
Expand All @@ -174,9 +175,10 @@
assign axi_wready = axi_wready_out;

// if both axi_awvalid_in=1 and axi_wvalid_in=1 then output axi_awready_out = 1 and axi_wready_out = 1
assign axi_awready_out = (axi_awvalid_in && axi_wvalid_in) ? 1 : 0;
assign axi_wready_out = (axi_awvalid_in && axi_wvalid_in) ? 1 : 0;
assign axi_awready_out = (axi_awvalid_in && axi_wvalid_in) ? 1'b1 : 1'b0;
assign axi_wready_out = (axi_awvalid_in && axi_wvalid_in) ? 1'b1 : 1'b0;

reg [1:0] is_as_tready_out;

//write register
always @(posedge axi_clk or negedge axi_reset_n) begin
Expand Down Expand Up @@ -266,29 +268,13 @@
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
reg [3:0] pre_as_is_tupsb_4_1_buf;
reg [(pDATA_WIDTH/8)-1:0] pre_as_is_tupsb_tlast_tvalid_tready_buf;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
reg [(pDATA_WIDTH/8)-1:0] pre_as_is_tlast_tvalid_tready_buf;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT

wire txen_rst_n = axis_rst_n & txen;

always @(negedge coreclk or negedge txen_rst_n) begin
pre_as_is_tdata_buf <= as_is_tdata;
pre_as_is_tstrb_buf <= as_is_tstrb;
pre_as_is_tkeep_buf <= as_is_tkeep;
pre_as_is_tid_tuser_buf[3:2] <= as_is_tid;
pre_as_is_tid_tuser_buf[1:0] <= as_is_tuser;
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tupsb_4_1_buf <= as_is_tupsb[pUSER_PROJECT_SIDEBAND_WIDTH-1:1];
pre_as_is_tupsb_tlast_tvalid_tready_buf[3] <= as_is_tupsb[0];
pre_as_is_tupsb_tlast_tvalid_tready_buf[2] <= as_is_tlast;
pre_as_is_tupsb_tlast_tvalid_tready_buf[1] <= as_is_tvalid;
pre_as_is_tupsb_tlast_tvalid_tready_buf[0] <= as_is_tready;
`else
pre_as_is_tlast_tvalid_tready_buf[2] <= as_is_tlast;
pre_as_is_tlast_tvalid_tready_buf[1] <= as_is_tvalid;
pre_as_is_tlast_tvalid_tready_buf[0] <= as_is_tready;
`endif

if ( !txen_rst_n ) begin
pre_as_is_tdata_buf <= 0;
Expand All @@ -298,25 +284,42 @@
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tupsb_4_1_buf <= 0;
pre_as_is_tupsb_tlast_tvalid_tready_buf <= 0;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tlast_tvalid_tready_buf <= 0;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT
end
else begin
if (is_as_tready && as_is_tvalid) begin //data transfer from Axis siwtch to io serdes when is_as_tready=1 and as_is_tvalid=1
pre_as_is_tdata_buf <= as_is_tdata;
pre_as_is_tstrb_buf <= as_is_tstrb;
pre_as_is_tkeep_buf <= as_is_tkeep;
pre_as_is_tid_tuser_buf[3:2] <= as_is_tid;
pre_as_is_tid_tuser_buf[1:0] <= as_is_tuser;
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tupsb_4_1_buf <= as_is_tupsb[pUSER_PROJECT_SIDEBAND_WIDTH-1:1];
pre_as_is_tupsb_tlast_tvalid_tready_buf[3] <= as_is_tupsb[0];
pre_as_is_tupsb_tlast_tvalid_tready_buf[2] <= as_is_tlast;
pre_as_is_tupsb_tlast_tvalid_tready_buf[1] <= as_is_tvalid;
pre_as_is_tupsb_tlast_tvalid_tready_buf[0] <= as_is_tready;
`else //USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tlast_tvalid_tready_buf[2] <= as_is_tlast;
pre_as_is_tlast_tvalid_tready_buf[1] <= as_is_tvalid;
pre_as_is_tlast_tvalid_tready_buf[0] <= as_is_tready;
`endif //USER_PROJECT_SIDEBAND_SUPPORT

if (is_as_tready_out[1] && as_is_tvalid) begin //data transfer from Axis siwtch to io serdes when is_as_tready=1 and as_is_tvalid=1

`ifdef USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tupsb_tlast_tvalid_tready_buf[1] <= as_is_tvalid;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tlast_tvalid_tready_buf[1] <= as_is_tvalid;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT
end
else begin
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tupsb_tlast_tvalid_tready_buf[1] <= 0; // set as_is_tvalid =0 to remote side
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
pre_as_is_tlast_tvalid_tready_buf[1] <= 0; // set as_is_tvalid =0 to remote side
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT

end
end
Expand All @@ -329,9 +332,9 @@
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
reg [pCLK_RATIO-1:0] as_is_tupsb_4_1_buf;
reg [pCLK_RATIO-1:0] as_is_tupsb_tlast_tvalid_tready_buf;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
reg [pCLK_RATIO-1:0] as_is_tlast_tvalid_tready_buf;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT

always @(posedge ioclk or negedge axis_rst_n) begin
if ( !axis_rst_n ) begin
Expand All @@ -342,9 +345,9 @@
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
as_is_tupsb_4_1_buf <= 0;
as_is_tupsb_tlast_tvalid_tready_buf <= 0;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
as_is_tlast_tvalid_tready_buf <= 0;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT
end
else begin
if (phase_cnt == 3) begin //update as_is_*_buf when phase_cnt == 3
Expand All @@ -355,9 +358,9 @@
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
as_is_tupsb_4_1_buf <= pre_as_is_tupsb_4_1_buf;
as_is_tupsb_tlast_tvalid_tready_buf <= pre_as_is_tupsb_tlast_tvalid_tready_buf;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
as_is_tlast_tvalid_tready_buf <= pre_as_is_tlast_tvalid_tready_buf;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT
end
end
end
Expand Down Expand Up @@ -408,20 +411,21 @@
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
assign Serial_Data_Out_tupsb_4_1 = as_is_tupsb_4_1_buf[tx_shift_phase_cnt] & txen ;
assign Serial_Data_Out_tupsb_tlast_tvalid_tready = as_is_tupsb_tlast_tvalid_tready_buf[tx_shift_phase_cnt] & txen ;
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
assign Serial_Data_Out_tlast_tvalid_tready = as_is_tlast_tvalid_tready_buf[tx_shift_phase_cnt] & txen ;
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT



// For Rx Path
`ifdef USER_PROJECT_SIDEBAND_SUPPORT
wire rxdata_out_valid[pSERIALIO_TDATA_WIDTH+3:0]; //add dummy connection to avoid WARNING message by xelab
`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
wire rxdata_out_valid[pSERIALIO_TDATA_WIDTH+2:0]; //add dummy connection to avoid WARNING message by xelab
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT

reg rxen;
assign rxen_out = rxen;

always @(negedge ioclk or negedge axis_rst_n) begin
if ( !axis_rst_n ) begin
Expand Down Expand Up @@ -537,7 +541,7 @@
.rxdata_out_valid(rx_received_data)
);

`else
`else //USER_PROJECT_SIDEBAND_SUPPORT
wire is_as_dummy;

fsic_io_serdes_rx #(
Expand All @@ -554,18 +558,20 @@
.rxdata_out( {is_as_dummy, is_as_tlast, is_as_tvalid, is_as_tready_remote}), // only connect [2:0]
.rxdata_out_valid(rx_received_data)
);
`endif
`endif //USER_PROJECT_SIDEBAND_SUPPORT

reg is_as_tready_out;
assign is_as_tready = is_as_tready_out;
assign is_as_tready = is_as_tready_out[0];

always @(posedge coreclk or negedge txen_rst_n ) begin
if ( !txen_rst_n ) begin
is_as_tready_out <= 0; //set is_as_tready_out=0 when txen == 0
end
else begin
if (rx_received_data == 0) is_as_tready_out <= 1; // when txen==1 and still not recevies data from remote side then set is_as_tready_out=1 to avoid dead lock issue.
else is_as_tready_out <= is_as_tready_remote; // when txen == 1 and rx_received_data==1 (received data from remote side) then is_as_tready_out come from is_as_tready_remote (remote side)
else begin
is_as_tready_out[0] <= is_as_tready_remote; // when txen == 1 and rx_received_data==1 (received data from remote side) then is_as_tready_out come from is_as_tready_remote (remote side)
is_as_tready_out[1] <= is_as_tready_out[0]; //is_as_tready_out[1] is delay 1T
end
end
end

Expand All @@ -574,3 +580,4 @@ endmodule




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