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update specification, AET relation diagram, and cheatsheet
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jan-ferdinand committed Feb 4, 2023
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Binary file modified specification/cheatsheet.pdf
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34 changes: 17 additions & 17 deletions specification/cheatsheet.tex
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\rowcolors{2}{row2}{row1}
\begin{tabular}{lllllllllllllllllllllll}
\toprule
Table & \multicolumn{5}{l}{Base Columns} & & & & & & & & & & & & & & & & & \\ \midrule
Program & \multicolumn{3}{l}{Address} & & \multicolumn{2}{l}{Instruction} & \multicolumn{4}{l}{LookupMultiplicity} & \multicolumn{3}{l}{IsPadding} & & & & & & & & & \\
Processor & \texttt{CLK} & IsPadding & \texttt{IP} & \texttt{PI} & \texttt{CI} & \texttt{NIA} & \texttt{IB0} & \dots & \texttt{IB7} & \texttt{JSP} & \texttt{JSO} & \texttt{JSD} & \texttt{ST0} & \dots & \texttt{ST15} & \texttt{OSP} & \texttt{OSV} & \texttt{HV0} & \dots & \texttt{HV3} & \texttt{RAMP} & \texttt{RAMV} \\
OpStack & \texttt{CLK} & \texttt{clk\_di} & & & & & & \multicolumn{4}{l}{\texttt{IB1} ($\widehat{=}$ shrink stack)} & & & & & \texttt{OSP} & \texttt{OSV} & & & & & \\
RAM & \texttt{CLK} & \texttt{clk\_di} & & \texttt{PI} & & \texttt{bcpc0} & \multicolumn{2}{l}{\texttt{bcpc1}} & & & & & & & & & & \multicolumn{3}{l}{\texttt{RAMP}DiffInv} & \texttt{RAMP} & \texttt{RAMV} \\
JumpStack & \texttt{CLK} & \texttt{clk\_di} & & & \texttt{CI} & & & & & \texttt{JSP} & \texttt{JSO} & \texttt{JSD} & & & & & & & & & & \\
Hash & \multicolumn{4}{l}{RoundNumber} & \texttt{CI} & & & & & & & & \texttt{ST0} & \dots & \texttt{ST15} & \multicolumn{3}{r}{\texttt{CONSTANT0A}} & \dots & \multicolumn{3}{l}{\texttt{CONSTANT15B}} \\
U32 & \texttt{CF} & \multicolumn{3}{l}{\texttt{Bits\quad Bits-33\_inv}} & \texttt{CI} & \texttt{LHS} & \texttt{RHS} & \texttt{LT} & \texttt{AND} & \texttt{XOR} & \multicolumn{2}{l}{\texttt{Log2Floor}} & \texttt{Pow} & \multicolumn{2}{l}{\texttt{LHS\_inv}} & \multicolumn{2}{l}{RHS\_inv} & & & & & \\ \bottomrule
Table & \multicolumn{5}{l}{Base Columns} & & & & & & & & & & & & & & & & & \\ \midrule
Program & \multicolumn{3}{l}{Address} & & \multicolumn{3}{l}{Instruction} & \multicolumn{4}{l}{LookupMultiplicity} & \multicolumn{3}{l}{IsPadding} & & & & & & & & \\
Processor & \texttt{CLK} & IsPadding & \texttt{IP} & \texttt{PI} & \texttt{CI} & \texttt{NIA} & \texttt{IB0} & \dots & \texttt{IB7} & \texttt{JSP} & \texttt{JSO} & \texttt{JSD} & \texttt{ST0} & \dots & \texttt{ST15} & \texttt{OSP} & \texttt{OSV} & \texttt{HV0} & \dots & \texttt{HV3} & \texttt{RAMP} & \texttt{RAMV} \\
OpStack & \texttt{CLK} & & & & & & & \multicolumn{4}{l}{\texttt{IB1} ($\widehat{=}$ shrink stack)} & & & & & \texttt{OSP} & \texttt{OSV} & & & & & \\
RAM & \texttt{CLK} & & & \texttt{PI} & & & \multicolumn{2}{l}{\texttt{bcpc0}} & \multicolumn{2}{l}{\texttt{bcpc1}} & & & & & & & & \multicolumn{3}{l}{\texttt{RAMP}DiffInv} & \texttt{RAMP} & \texttt{RAMV} \\
JumpStack & \texttt{CLK} & & & & \texttt{CI} & & & & & \texttt{JSP} & \texttt{JSO} & \texttt{JSD} & & & & & & & & & & \\
Hash & \multicolumn{4}{l}{RoundNumber} & \texttt{CI} & & & & & & & & \texttt{ST0} & \dots & \texttt{ST15} & \multicolumn{3}{r}{\texttt{CONSTANT0A}} & \dots & \multicolumn{3}{l}{\texttt{CONSTANT15B}} \\
U32 & \texttt{CF} & \multicolumn{3}{l}{\texttt{Bits\quad Bits-33\_inv}} & \texttt{CI} & \texttt{LHS} & \texttt{RHS} & \texttt{LT} & \texttt{AND} & \texttt{XOR} & \multicolumn{2}{l}{\texttt{Log2Floor}} & \texttt{Pow} & \multicolumn{2}{l}{\texttt{LHS\_inv}} & \multicolumn{2}{l}{RHS\_inv} & & & & & \\ \bottomrule
\end{tabular}
} %end scalebox
\begin{tikzpicture}[remember picture, overlay]
Expand All @@ -119,12 +119,12 @@
& base & ext & $\sum$ \\ \midrule
Program & 4 & 1 & 5 \\
Processor & 44 & 13 & 57 \\
OpStack & 5 & 2 & 7 \\
RAM & 8 & 6 & 14 \\
JumpStack & 6 & 2 & 8 \\
OpStack & 4 & 2 & 6 \\
RAM & 7 & 6 & 13 \\
JumpStack & 5 & 2 & 7 \\
Hash & 50 & 3 & 53 \\
U32 & 14 & 1 & 15 \\ \bottomrule\bottomrule
$\sum$ & 131 & 28 & 159
$\sum$ & 128 & 28 & 156
\end{tabular}
\end{minipage}%
\hfill%
Expand All @@ -148,14 +148,14 @@
\toprule
& init & cons & trans & term & $\sum$ \\ \midrule
Program & 2 & 1 & 3 & & 6 \\
Processor & 39 & 12 & 77 & 2 & 130 \\
OpStack & 5 & & 6 & & 11 \\
Ram & 8 & & 14 & 1 & 23 \\
JumpStack & 6 & & 8 & & 14 \\
Processor & 39 & 13 & 75 & 1 & 128 \\
OpStack & 5 & & 4 & & 9 \\
Ram & 8 & & 12 & 1 & 21 \\
JumpStack & 6 & & 6 & & 12 \\
Hash & 5 & 40 & 26 & & 71 \\
U32 & 2 & 14 & 22 & 2 & 40 \\
Cross-Table & & & & 1 & 1 \\ \bottomrule\bottomrule
$\sum$ & 67 & 67 & 156 & 6 & 296
$\sum$ & 67 & 68 & 148 & 5 & 288
\end{tabular}
\end{minipage}

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200 changes: 87 additions & 113 deletions specification/src/img/aet-relations.ipe
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