added fpga code and design for biosafety cabinet

.github/workflows/discord_notification.yml

@@ -0,0 +1,27 @@
+name: Send discord notification
+on: [push]
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Checkout code
+      uses: actions/checkout@v2
+
+    - name: Send Discord notification to Server 1
+      env:
+        DISCORD_WEBHOOK_ID: ${{ secrets.DISCORD_WEBHOOK_ID }}
+        DISCORD_WEBHOOK_TOKEN: ${{ secrets.DISCORD_WEBHOOK_TOKEN }}
+      run: |
+        COMMIT_MESSAGE=$(git log -1 --pretty=format:"%s")
+        COMMIT_DESCRIPTION=$(git log -1 --pretty=format:"%b")
+        curl -X POST -H "Content-Type: application/json" -d "{ \"content\": \"New commit! Check out the latest changes: https://github.com/Unlimited-Research-Cooperative/Human-Brain-Rat/commits/${{ github.sha }}\", \"embeds\": [ { \"title\": \"$COMMIT_MESSAGE\", \"description\": \"$COMMIT_DESCRIPTION\" } ] }" https://discord.com/api/webhooks/$DISCORD_WEBHOOK_ID/$DISCORD_WEBHOOK_TOKEN
+
+    - name: Send Discord notification to Server 2
+      env:
+        URC_WEBHOOK_ID: ${{ secrets.URC_WEBHOOK_ID }}
+        URC_WEBHOOK_TOKEN: ${{ secrets.URC_WEBHOOK_TOKEN }}
+      run: |
+        COMMIT_MESSAGE=$(git log -1 --pretty=format:"%s")
+        COMMIT_DESCRIPTION=$(git log -1 --pretty=format:"%b")
+        curl -X POST -H "Content-Type: application/json" -d "{ \"content\": \"New commit! Check out the latest changes: https://github.com/Unlimited-Research-Cooperative/Human-Brain-Rat/commits/${{ github.sha }}\", \"embeds\": [ { \"title\": \"$COMMIT_MESSAGE\", \"description\": \"$COMMIT_DESCRIPTION\" } ] }" https://discord.com/api/webhooks/$URC_WEBHOOK_ID/$URC_WEBHOOK_TOKEN

Code_FPGA_DAC_ADC/brain_to_computer/CycloneIV/Factory code/AX301_BOOT_PRJ/AX301_BOOT_SDRAM.qarlog

@@ -0,0 +1,64 @@
+Quartus Prime Archive log --	D:/intel_project/AX301/AX301_BOOT_PRJ_restored/AX301_BOOT_SDRAM.qarlog
+
+Archive:	D:/intel_project/AX301/AX301_BOOT_PRJ_restored/AX301_BOOT_SDRAM.qar
+Date:		Wed Mar 28 08:57:10 2018
+Quartus Prime		17.1.0 Build 590 10/25/2017 SJ Lite Edition
+
+	=========== Files Selected: ===========
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/SDC1.sdc
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/assignment_defaults.qdf
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ax301_ax4010.tcl
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ax_debounce.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/buzzer_src/music_hz.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/buzzer_src/music_rom.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/buzzer_src/music_top.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/buzzer_src/sin512.mif
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/db/stp1_auto_stripped.stp
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/eeprom_src/i2c_eeprom_test.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/eeprom_src/key_debounce.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/i2c_master/i2c_config.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/i2c_master/i2c_master_bit_ctrl.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/i2c_master/i2c_master_byte_ctrl.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/i2c_master/i2c_master_defines.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/i2c_master/i2c_master_top.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/i2c_master/timescale.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/output_files/stp1.stp
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/cmos_8_16bit.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/cmos_write_req_gen.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/color_bar.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/frame_fifo_read.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/frame_fifo_write.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/frame_read_write.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/ip_core/afifo_16_512.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/ip_core/sys_pll.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/ip_core/video_pll.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/lut_ov5640_rgb565_1024_768.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/sdram/sdram_core.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/top.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/video_define.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/ov5640_src/video_timing_data.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/rtc_src/ds1302.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/rtc_src/ds1302_io.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/rtc_src/ds1302_test.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/rtc_src/seg_bcd.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/rtc_src/top.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/sdbmp_src/bmp_read.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/sdbmp_src/sd_card/sd_card_cmd.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/sdbmp_src/sd_card/sd_card_sec_read_write.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/sdbmp_src/sd_card/sd_card_top.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/sdbmp_src/sd_card_bmp.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/sdbmp_src/top.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/seg_src/seg_decoder.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/seg_src/seg_scan.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/spi_master.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/top.qpf
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/top.qsf
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/top.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/total.tcl
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/uart_src/uart_rx.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/uart_src/uart_test.v
+D:/intel_project/AX301/AX301_BOOT_PRJ_restored/uart_src/uart_tx.v
+	======= Total: 53 files to archive =======
+
+	================ Status: ===============
+All files archived successfully.

Code_FPGA_DAC_ADC/brain_to_computer/CycloneIV/Factory code/AX301_BOOT_PRJ/SDC1.sdc

@@ -0,0 +1,45 @@
+create_clock -name clk -period 20 [get_ports {clk}]
+
+create_clock -name cmos_clk -period 15.38 [get_ports {cmos_pclk}]
+
+
+
+
+derive_pll_clocks -create_base_clocks
+
+
+set_false_path -from [get_clocks {cmos_clk}] -to [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}]
+set_false_path -from [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {cmos_clk}]
+
+set_false_path -from [get_clocks {video_pll_m0|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}]
+set_false_path -from [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {video_pll_m0|altpll_component|auto_generated|pll1|clk[0]}]
+
+#set_false_path -from [get_clocks {clk}] -to [get_clocks {video_pll_m0|altpll_component|auto_generated|pll1|clk[0]}]
+#set_false_path -from [get_clocks {video_pll_m0|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {clk}]
+#
+#set_false_path -from [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {clk}]
+#set_false_path -from [get_clocks {clk}] -to [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[0]}]
+
+set_false_path -from [get_clocks {clk}] -to [get_clocks {video_pll_m0|altpll_component|auto_generated|pll1|clk[0]}]
+set_false_path -from [get_clocks {video_pll_m0|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {clk}]
+
+set_false_path -from [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[0]}]
+set_false_path -from [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}]
+
+#set_false_path -from {sdbmp_rst_n} -to {sdbmp_top:sdbmp_dut|sd_card_bmp:sd_card_bmp_m0|bmp_read:bmp_read_m0|width[*]}
+#set_false_path -from {sdbmp_top:sdbmp_dut|sd_card_bmp:sd_card_bmp_m0|bmp_read:bmp_read_m0|state_code[*]} -to {sdbmp_top:sdbmp_dut|seg_scan:seg_scan_m0|seg_data[*]}
+#set_false_path -from {ax_debounce:ax_debounce_a2|button_negedge} -to {current_state.idle}
+#set_false_path -from {ax_debounce:ax_debounce_a2|button_negedge} -to {current_state.sd_mode}
+#
+#set_false_path -from {ax_debounce:ax_debounce_a2|button_negedge} -to {sdram_rst_n}
+#set_false_path -from {ax_debounce:ax_debounce_a2|button_negedge} -to {current_state.ledflash_mode}
+#set_false_path -from {ax_debounce:ax_debounce_a2|button_negedge} -to {current_state.eeprom_mode}
+
+set_false_path -from [get_clocks {clk}] -to [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[0]}]
+set_false_path -from [get_clocks {sys_pll_m0|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {clk}]
+
+
+set_false_path -from [get_clocks {clk}] -to [get_clocks {cmos_clk}]
+set_false_path -from [get_clocks {cmos_clk}] -to [get_clocks {clk}]
+
+

Code_FPGA_DAC_ADC/brain_to_computer/CycloneIV/Factory code/AX301_BOOT_PRJ/SDC1.sdc.bak

@@ -0,0 +1,15 @@
+create_clock -name clk -period 20 [get_ports {clk}]
+
+create_clock -name cmos_clk -period 15.38 [get_ports {cmos_pclk}]
+
+
+
+
+derive_pll_clocks -create_base_clocks
+
+
+set_false_path -from [get_clocks {cmos_clk}] -to [get_clocks {sdbmp_dut|sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}]
+set_false_path -from [get_clocks {sdbmp_dut|sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {cmos_clk}]
+
+set_false_path -from [get_clocks {video_pll_m0|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sdbmp_dut|sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}]
+set_false_path -from [get_clocks {sdbmp_dut|sys_pll_m0|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {video_pll_m0|altpll_component|auto_generated|pll1|clk[0]}]