Save Changes & Submit

output.log

@@ -0,0 +1,17 @@
+Test passed
+Test passed
+Left barrel shifter test passed
+Warning: file 'v1.hex' for memory 'a_memory' has a gap at addresses 64 to 255.
+Warning: file 'v2.hex' for memory 'b_memory' has a gap at addresses 64 to 255.
+STARTING TEST FOR VECTOR DOT PRODUCT DIM 16... index 0
+GOT        410
+Test 0 passed
+STARTING TEST FOR VECTOR DOT PRODUCT DIM 16... index 1
+GOT        354
+Test 1 passed
+STARTING TEST FOR VECTOR DOT PRODUCT DIM 16... index 2
+GOT        524
+Test 2 passed
+STARTING TEST FOR VECTOR DOT PRODUCT DIM 16... index 3
+GOT        410
+Test 3 passed

output1.log

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+Test passed

output2.log

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+Test passed

output3.log

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+Left barrel shifter test passed

output4.log

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+Warning: file 'v1.hex' for memory 'a_memory' has a gap at addresses 64 to 255.
+Warning: file 'v2.hex' for memory 'b_memory' has a gap at addresses 64 to 255.
+STARTING TEST FOR VECTOR DOT PRODUCT DIM 16... index 0
+GOT        410
+Test 0 passed
+STARTING TEST FOR VECTOR DOT PRODUCT DIM 16... index 1
+GOT        354
+Test 1 passed
+STARTING TEST FOR VECTOR DOT PRODUCT DIM 16... index 2
+GOT        524
+Test 2 passed
+STARTING TEST FOR VECTOR DOT PRODUCT DIM 16... index 3
+GOT        410
+Test 3 passed

part_1_combinational/AluTest

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+#!/bin/sh
+
+BLUESPECDIR=`echo 'puts $env(BLUESPECDIR)' | bluetcl`
+
+for arg in $@
+do
+  if (test "$arg" = "-h")
+  then
+    exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTest --script_name `basename $0` -h
+  fi
+done
+exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTest --script_name `basename $0` --creation_time 1708621743 "$@"

part_1_combinational/ArbiterTest

@@ -0,0 +1,12 @@
+#!/bin/sh
+
+BLUESPECDIR=`echo 'puts $env(BLUESPECDIR)' | bluetcl`
+
+for arg in $@
+do
+  if (test "$arg" = "-h")
+  then
+    exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTest --script_name `basename $0` -h
+  fi
+done
+exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTest --script_name `basename $0` --creation_time 1708621745 "$@"

part_1_combinational/ShifterTest

@@ -0,0 +1,12 @@
+#!/bin/sh
+
+BLUESPECDIR=`echo 'puts $env(BLUESPECDIR)' | bluetcl`
+
+for arg in $@
+do
+  if (test "$arg" = "-h")
+  then
+    exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTest --script_name `basename $0` -h
+  fi
+done
+exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTest --script_name `basename $0` --creation_time 1708621747 "$@"

part_1_combinational/build/mkTest.h

@@ -0,0 +1,124 @@
+/*
+ * Generated by Bluespec Compiler, version 2023.07-39-g15463f50 (build 15463f50)
+ * 
+ * On Thu Feb 22 18:09:07 CET 2024
+ * 
+ */
+
+/* Generation options: */
+#ifndef __mkTest_h__
+#define __mkTest_h__
+
+#include "bluesim_types.h"
+#include "bs_module.h"
+#include "bluesim_primitives.h"
+#include "bs_vcd.h"
+
+
+/* Class declaration for the mkTest module */
+class MOD_mkTest : public Module {
+
+ /* Clock handles */
+ private:
+  tClock __clk_handle_0;
+
+ /* Clock gate handles */
+ public:
+  tUInt8 *clk_gate[0];
+
+ /* Instantiation parameters */
+ public:
+
+ /* Module state */
+ public:
+  MOD_Reg<tUInt32> INST_ctr_fsm;
+  MOD_Reg<tUInt8> INST_going;
+  MOD_Wire<tUInt8> INST_test_fsm_abort;
+  MOD_Reg<tUInt8> INST_test_fsm_start_reg;
+  MOD_Reg<tUInt8> INST_test_fsm_start_reg_1;
+  MOD_Wire<tUInt8> INST_test_fsm_start_reg_2;
+  MOD_Wire<tUInt8> INST_test_fsm_start_wire;
+  MOD_Reg<tUInt8> INST_test_fsm_state_can_overlap;
+  MOD_Reg<tUInt8> INST_test_fsm_state_fired;
+  MOD_Wire<tUInt8> INST_test_fsm_state_fired_1;
+  MOD_ConfigReg<tUInt8> INST_test_fsm_state_mkFSMstate;
+  MOD_Wire<tUInt8> INST_test_fsm_state_overlap_pw;
+  MOD_Wire<tUInt8> INST_test_fsm_state_set_pw;
+  MOD_RegFile<tUInt8,tUWide> INST_tests;
+  MOD_Reg<tUInt8> INST_verbose;
+
+ /* Constructor */
+ public:
+  MOD_mkTest(tSimStateHdl simHdl, char const *name, Module *parent);
+
+ /* Symbol init methods */
+ private:
+  void init_symbols_0();
+
+ /* Reset signal definitions */
+ private:
+  tUInt8 PORT_RST_N;
+
+ /* Port definitions */
+ public:
+
+ /* Publicly accessible definitions */
+ public:
+  tUInt8 DEF_WILL_FIRE_RL_test_fsm_action_l30c9;
+  tUInt8 DEF_WILL_FIRE_RL_test_fsm_action_l17c13;
+  tUInt8 DEF_WILL_FIRE_RL_test_fsm_action_l13c10;
+  tUInt32 DEF_x__h13119;
+
+ /* Local definitions */
+ private:
+  tUWide DEF_tests_sub_ctr_fsm_7_BITS_3_TO_0_5___d46;
+
+ /* Rules */
+ public:
+  void RL_test_fsm_start_reg__dreg_update();
+  void RL_test_fsm_state_handle_abort();
+  void RL_test_fsm_state_fired__dreg_update();
+  void RL_test_fsm_state_every();
+  void RL_test_fsm_restart();
+  void RL_test_fsm_action_l13c10();
+  void RL_test_fsm_action_l17c13();
+  void RL_test_fsm_action_l30c9();
+  void RL_test_fsm_idle_l12c7();
+  void RL_test_fsm_fsm_start();
+  void RL_start();
+  void __me_check_5();
+  void __me_check_6();
+
+ /* Methods */
+ public:
+
+ /* Reset routines */
+ public:
+  void reset_RST_N(tUInt8 ARG_rst_in);
+
+ /* Static handles to reset routines */
+ public:
+
+ /* Pointers to reset fns in parent module for asserting output resets */
+ private:
+
+ /* Functions for the parent module to register its reset fns */
+ public:
+
+ /* Functions to set the elaborated clock id */
+ public:
+  void set_clk_0(char const *s);
+
+ /* State dumping routine */
+ public:
+  void dump_state(unsigned int indent);
+
+ /* VCD dumping routines */
+ public:
+  unsigned int dump_VCD_defs(unsigned int levels);
+  void dump_VCD(tVCDDumpType dt, unsigned int levels, MOD_mkTest &backing);
+  void vcd_defs(tVCDDumpType dt, MOD_mkTest &backing);
+  void vcd_prims(tVCDDumpType dt, MOD_mkTest &backing);
+};
+
+#endif /* ifndef __mkTest_h__ */