VHDL block diagrams using netlistsvg

[nobodywasishere]

ref: https://nobodywasishere.github.io/netlistsvg/
tags: [VHDL, netlistsvg]
related: [17]

Block diagrams are a useful way of presenting state machines and other HDL code in a visual manner. They are useful for learning how the code works, documenting it for future programmers and reports, or debugging code that may not be working as expected.

While tools for generating block diagrams are already included in most HDL development environments, these are typically proprietary (though they may be free as in beer, they’re not free as in freedom). Here is how to generate a block diagram from VHDL using netlistsvg and the open source FPGA toolchain on Linux.

[eine]

Related:

• Sphinx extension: SymbiFlow/sphinxcontrib-hdl-diagrams.
• Convert (V)HDL to other formats (How to convert vhdl to other formats #17)