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studying
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Achievement: Starstruck

Achievements

Achievement: Starstruck

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VardhanSuroshi/README.md

Typing SVG

💫 About Me:

Coding

Hey there! I'm Vardhan, the final-year B.Tech ninja at PES University.



You can find me buried under a pile of paper & books📚, sipping tea🍵, and occasionally questioning❓my life choices.

I work with cool folks at CHIPS on making chips💻 that don't just snack on energy but also do a mean moonwalk in efficiency. Think of it as my way of making circuits eco-friendly♻️.

I'm that guy who finds joy in VLSI and thinks digital design is cooler than a <some_adjective>!! I'm basically a digital design enthusiast, turning 1s and 0s into magic spells

You can Reach me at:

www.linkedin.com/in/vardhansuroshi

💻 Tools I wield like a wizard:

arduino    sv    sv    c    linux    matlab    python    openroad    cadence   

Check out my projects:

1. VLSI ASIC Design Flow

  • Ever wanted to dive deep into the magical world of VLSI design? Well, you're in luck! This repository is dedicated to VLSI ASIC Design Flow using open-source tools!
  • Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

2. VLSI Physical Design

  • This project offers an immersive tutorial experienced within the context of the Advanced Physical Design. This repo is the continuity of VLSI ASIC Design Flow.
  • Armed with nothing but my trusty keyboard and a lot of tea. In this adventure, we'll explore the Opensource ASIC Design tool OpenLANE and emerge victorious!

3. 16-bit SRAM using Cadence Tool-chain

  • This project involves the designing of a 4X4 (16-bit) SRAM Memory Array and peripheral logics using Cadence Virtuoso.
  • It's like playing with LEGOs, but way cooler😎 and with a lot more frustration!

4. प्रयास (Prayaas)

  • प्रयास is a 32-bit RISC-V I-type processor! {Work in progress } Currently on a ride designing, writing coding, debugging, and reaching existential crises.
  • Will it work? Who knows! But hey, it's the journey that counts, right?

Also do check out my, "not so cool" projects here

📊 GitHub Stats:

Pinned Loading

  1. Memory-Design-And-Testing Memory-Design-And-Testing Public

    The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso

    16 2

  2. VLSI-ASIC-Design-Flow VLSI-ASIC-Design-Flow Public

    This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally …

    Verilog 6 2